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| PRELIMINARY DATA SHEET MICRONAS MAS 3587F MPEG Layer 3 Audio Encoder/Decoder Edition Nov. 7, 2001 6251-542-2PD MICRONAS MAS 3587F Contents Page 5 5 6 7 7 7 7 7 8 8 9 9 9 9 9 10 10 10 10 10 11 11 11 11 11 12 14 14 15 15 15 15 15 15 15 16 16 16 16 17 17 17 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.7. 2.7.1. 2.7.1.1. 2.7.2. 2.7.2.1. 2.7.2.2. 2.7.3. 2.7.4. 2.8. 2.8.1. 2.8.2. 2.9. 2.9.1. 2.9.2. 2.9.3. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.11.5. 2.11.6. 2.12. 2.13. 2.13.1. 2.13.2. 2.13.3. 2.13.4. 2.13.5. Title Introduction Features Application Overview PRELIMINARY DATA SHEET Functional Description Overview Architecture of the MAS 3587F DSP Core RAM and Registers Firmware and Software Internal Program ROM and Firmware, MPEG-Encoding/Decoding Program Download Feature Audio Codec A/D Converter and Microphone Amplifier Baseband Processing Bass, Treble, and Loudness Micronas Dynamic Bass (MDB) Automatic Volume Correction (AVC) Balance and Volume D/A Converters Output Amplifiers Clock Management DSP Clock Clock Output at CLKO Power Supply Concept Power Supply Regions DC/DC Converters Power Supply Configurations Battery Voltage Supervision Interfaces I2C Control Interface S/PDIF Input Interface S/PDIF Output Multiline Serial Audio Input (SDI, SDIB) Multiline Serial Output (SDO) Parallel Input/Output Interface (PIO) MPEG Synchronization Output Default Operation Stand-by Functions Power-Up of the DC/DC Converters and Reset Control of the Signal Processing Start-up of the Audio Codec Power-Down 2 Micronas PRELIMINARY DATA SHEET MAS 3587F Contents, continued Page 18 18 18 18 19 20 20 20 23 23 23 24 25 25 25 25 26 26 26 26 26 27 27 28 28 28 29 37 37 38 38 38 39 39 40 40 40 41 46 47 47 48 51 51 51 51 Section 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.2. 3.2.1. 3.2.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.3.2.8. 3.3.2.9. 3.3.2.10. 3.3.2.11. 3.3.2.12. 3.3.3. 3.3.4. 3.3.4.1. 3.3.4.2. 3.3.5. 3.3.5.1. 3.3.5.2. 3.3.6. 3.3.7. 3.3.7.1. 3.3.8. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. Title Controlling I2C Interface Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Data Formats Run and Freeze (Codes 0hex to 3hex) Read Register (Code Ahex) Write Register (Code Bhex) Read Memory (Codes Chex and Dhex) Short Read Memory (Codes C4hex and D4hex) Write Memory (Codes Ehex and Fhex) Short Write Memory (Codes E4hex and F4hex) Clear SYNC Signal (Code 5hex) Default Read Fast Program Download (Code 6hex) Serial Program Download Read IC Version (Code 7hex) List of DSP Registers List of DSP Memory Cells Application Selection and Application Running Application Specific Control Copyright Management Encoding of Analog or PCM-Audio Decoding Variable Bitrate Encoding Ancillary Data Timecode Information DSP Volume Control Audio Codec Access Protocol Write Codec Register Read Codec Register Codec Registers Basic MDB Configuration Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Reference Pins DC/DC Converters and Battery Voltage Supervision Micronas 3 MAS 3587F Contents, continued Page 51 51 51 52 52 52 52 52 52 52 52 53 53 54 56 56 57 61 62 63 65 67 68 69 70 71 72 76 78 81 82 84 Section 4.3.4. 4.3.5. 4.3.6. 4.3.6.1. 4.3.7. 4.3.8. 4.3.9. 4.3.10. 4.3.11. 4.3.12. 4.3.13. 4.3.14. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.4. 4.6.5. 4.6.6. 4.7. 4.8. 5. Title Oscillator Pins and Clocking Control Lines Parallel Interface Lines PIO Handshake Lines Serial Input Interface (SDI) Serial Input Interface B (SDIB) Serial Output Interface (SDO) S/PDIF Input Interface S/PDIF Output Interface Analog Input Interfaces Analog Output Interfaces Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Digital Characteristics I2C Characteristics Serial (I2S) Input Interface Characteristics (SDI, SDIB) Serial Output Interface Characteristics (SDO) S/PDIF Input Characteristics S/PDIF Output Characteristics PIO as Parallel Input Interface: DMA Mode PIO As Parallel Input Interface: Program Download Mode PIO as Parallel Output Interface: DMA Mode Analog Characteristics DC/DC Converter Characteristics Typical Performance Characteristics Typical Application in a Portable Player Recommended DC/DC Converter Application Circuit Data Sheet History PRELIMINARY DATA SHEET License Notices Supply of this product only conveys a license for private, non-commercial use and does not convey a license nor imply any right to use this product in real time broadcasting (terrestrial, satellite, cable and/or any other media) or broadcasting via Internet and/or other networks, including, but not limited to, intranets or in pay-audio or audio-ondemand applications. An independendent license for such use is required. For details, please visit http://www.mp3licensing.com. MPEG Layer-3 audio coding technology licensed by Fraunhofeer IIS (http://www.iis.fhg.de/audio/) 4 Micronas PRELIMINARY DATA SHEET MAS 3587F 1.1. Features Firmware - MPEG 1/2 layer 3 encoder - Encoding with adaptive bit rate up to 192 kbit/s - MPEG 1/2 layer 2 and layer 3 decoder MPEG Layer 3 Audio Encoder/Decoder This data sheet applies to MAS 3587F version B2. Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The MAS 3587F is a single-chip MPEG layer 3 audio encoder/decoder designed for use in memory-based recording/playback applications, e.g. MP3 record/playback equipment. The IC contains a DSP engine with embedded RAM and ROM. It provides flexible digital interfaces for serial and S/PDIF audio data input and output. Also integrated are power management functions and two DC/DC converters for single cell power supply. A high-quality stereo D/A converter and a stereo A/D converter on chip provide the analog functions required in an advanced portable audio player. In encoding mode, audio data is input via the integrated A/D converter, serial PCM, or S/PDIF interface. The compressed digital data stream is sent via the parallel interface. In decoding mode, compressed digital data streams are accepted in the parallel or serial format. The audio data is output via the high quality D/A converter. A digital output in serial PCM format and/or S/PDIF format is also provided. Thus, the MAS 3587F provides a true 'ALL-IN-ONE' solution that is ideally suited for highly optimized memory based music recorders. Additional functionality is achieved via download software (e.g. Micronas SC4 encoder/decoder). SC4 is a proprietary Micronas speech codec technology based on ADPCM. The codec can be downloaded to the MAS 3587F to allow high quality speech recording and playing back at various sampling rates. (Please contact your local Micronas Sales Representative about availability of SC4 downloads). In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. The MAS 3587F is available in the PMQFP64 package. - Decoder-extension to MPEG 2 layer 3 for low bit rates ("MPEG 2.5") - Extraction of MPEG Ancillary Data - Adaptive bit rates (bit rate switching) - SDMI-compliant security technology for decoder - Stereo channel mixer - Bass, treble and loudness function - Micronas Dynamic Bass (MDB) - Automatic Volume Correction (AVC) Interfaces - 2 serial asynchronous interfaces for bitstreams and uncompressed digital audio - Parallel handshake bit stream input/output - Serial audio output via I2S and related formats - S/PDIF audio input - S/PDIF audio output - Controlling via I2C interface Hardware Features - Two independent embedded DC/DC converters (e.g. for DSP and flash RAM supply) - Low DC/DC converter start-up voltage (0.9 V) - DC converter efficiency up to 95% - Battery voltage monitor - Low supply voltage (down to 2.5 V for decoder, 3.5 V for encoder) - Low power dissipation (down to 70 mW for decoder, down to 450 mW for MPEG 1 encoder) - Hardware power management and power-off functions - Microphone amplifier - Stereo A/D converter for FM/AM-radio and speech input - CD quality stereo D/A converter - Headphone amplifier - On-chip crystal oscillator - External clock or crystal frequency of 13...28 MHz - Standby current < 10 A Micronas 5 MAS 3587F 1.2. Application Overview The following block diagram shows an example application for the MAS 3587F in a portable audio recorder device. Besides a simple controller and the external flash memories, all required components are integrated in the MAS 3587F. By means of the embedded A/D-converter, the MAS 3587F supports both speech and FM radio quality audio encoding. CD-quality encoding/decoding is achieved by using digital inputs/embedded D/A-converter. PRELIMINARY DATA SHEET Fig. 1-1 depicts a portable audio application that is power optimized. The two embedded DC/DC converters of the MAS 3587F generate optimum power supply voltages for the DSP core and also for state-of-the-art flash memories that typically require 2.7 to 3.3 V supply. The performance of the DC/DC converters reaches efficiencies up to 95%. 3RUWDEOH 'LJLWDO 0XVLF 5HFRUGHU 0$6 ) line in Audio baseband features '63 &RUH Microphone amplifier MP3 encoding/ decoding Optional Software Downloads Headphone amplifier Volume Headphone A/D D/A optional digital in S/PDIF or serial digital out S/PDIF or serial Crystal Osc./PLL I2C DC/DC1 DC/DC2 Parallel I/O Bus System clock I2C Control e.g. 2.7 V e.g. 3.5 V / 2.5 V I2C Display Keyboard C PC Connector Fig. 1-1: Example application for the MAS 3587F in a portable audio recorder device 6 Flash RAM Micronas PRELIMINARY DATA SHEET MAS 3587F 2.3. DSP Core The internal processor is a dedicated DSP for advanced audio applications. 2. Functional Description 2.1. Overview The MAS 3587F is intended for use in consumer audio applications. It encodes analog audio input, PCM data or S/PDIF signals to variable bit rate MPEG 1/2 Layer 3 data streams. The compressed data is stored in an external memory via the parallel port. For playback it receives parallel or serial data streams and decodes MPEG Layer 2 and 3 (including the low sampling frequency extensions). 2.4. RAM and Registers The DSP core has access to two RAM banks denoted D0 and D1. All RAM addresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For fast access of internal DSP states the processor core has an address space of 256 data registers which can be accessed by I2C bus. For more details please refer to Section 3.3. on page 23. 2.2. Architecture of the MAS 3587F The hardware of the MAS 3587F consists of a highperformance RISC Digital Signal Processor (DSP), and appropriate interfaces. A hardware overview of the IC is shown in Fig. 2-1. Mic. Input (incl. Bias) 1 Line Input 2 Audio Codec 2 A/D MIX Audio Proc. D/A 2 Audio Output DSP Core S/PDIF Input 1 S/PDIF Input 2 Serial Audio (I S, SDI) 2 ALU MAC Serial Audio (I2S, SDO) Accumulators ROM Output Select Input Select S/PDIF Output Control DCCF DCFR DSP Codec Serial Audio (stream, SDIB) VBAT Volt. Mon. D0 D1 IC Interface 2 I2C control V1 DC/DC 2 DC/DC 1 Registers Div. Div. V2 Parallel I/O Bus (PIO) Xtal 18.432 MHz Osc. PLL Synth. Synthesizer Clock Scaler /2 CLKO Fig. 2-1: The MAS 3587F architecture Micronas 7 MAS 3587F 2.5. Firmware and Software 2.5.1. Internal Program ROM and Firmware, MPEG-Encoding/Decoding The firmware implemented in the program ROM of the MAS 3587F provides MPEG 1/2 Layer 3 encoding and decoding of MPEG 1/2 Layer 2 and MPEG 1/2 Layer 3. The DSP operating system starts the firmware in the "Application Selection Mode". By setting the appropriate bit in the Application Select memory cell (see Table 3-7 on page 28), the MPEG audio encoder or decoder can be activated. PRELIMINARY DATA SHEET The MPEG decoder provides an automatic standard detection mode. If all MPEG audio decoders are selected, the Layer 2 or Layer 3 bitstream is recognized and decoded automatically. For general control purposes, the operation system provides a set of I2C instructions that give access to internal DSP registers and memory areas. An auxiliary digital volume control and mixer matrix is applied to the digital stereo audio data. This matrix is capable of performing the balance control and a simple kind of stereo basewidth enhancement. All four factors LL, LR, RL, and RR are adjustable, please refer to Fig. 3-3 on page 39. S/PDIF Do:7f2 S/PDIF2 Encoder SDI D0:7f1 PIO S/PDIF D0:7f1 SDO Audio Proc. LINE IN MIC IN A/D MIX D/A OUT Fig. 2-2: Encoder Signal Flow (Reset setting shown) PIO D0:7f1 Decoder SDIB DSP Volume Matrix S/PDIF SDO LINE IN MIC IN A/D MIX Audio Proc. D/A OUT Fig. 2-3: Decoder Signal Flow (Reset setting shown) 8 Micronas PRELIMINARY DATA SHEET MAS 3587F 2.7. A/D Converter and Microphone Amplifier A pair of A/D converters is provided for recording or loop-through purposes. In addition, a microphone amplifier including voltage supply function for an electret type microphone has been integrated. 2.5.2. Program Download Feature The standard functions of the MAS 3587F can be extended or substituted by downloading up to 4 kWords (1 Word = 20 bits) of program code and additionally up to 4 kWords of coefficients into the internal RAM. The code must be downloaded by the Fast Program Download command (see Section 3.3.2.10. on page 26) into an area of RAM that is switchable from data memory to program memory. A Run command (see Section 3.3.2.1. on page 24) starts the operation. 2.7.1. Baseband Processing Several baseband functions are applied to the digital audio signal immediately before D/A conversion. 2.7.1.1. Bass, Treble, and Loudness 2.6. Audio Codec A sophisticated set of audio converters and sound features has been implemented to comply with various kinds of operating environments that range up to highend equipment (see Fig. 2-4). Mic-In Mic-Amplifier incl. Bias Deemphasis 50s / 75s Standard baseband functions such as bass, treble, and loudness are provided (refer to Table 3-17 for details). Amplitude 10 A D A D Q-peak Mono/Stereo Q-peak AVC Bass/Treble Headphone Amplifier Mono [dB] 5 DSP 0 Line-In Mixer -5 -10 100 f [Hz] 1000 10000 Audio Codec D A D A Volume Balance Loudness MDB Right invert Fig. 2-5: Bass Frequency Response Amplitude 10 5 [dB] Output Fig. 2-4: Signal flow block diagram of the Audio Codec 0 -5 -10 100 f [Hz] Fig. 2-6: Treble Frequency Response 1000 10000 Micronas 9 MAS 3587F PRELIMINARY DATA SHEET 2.7.2.2. Balance and Volume Amplitude 10 [dB] To minimize quantization noise, the main volume control is automatically split into a digital and an analog part. The volume range is -114...+12 dB with an additional mute position. A balance function is provided (see Table 3-17). 5 0 -5 -10 100 f [Hz] 1000 10000 2.7.3. D/A Converters A pair of Micronas' unique multibit sigma-delta D/A converters is used to convert the audio data with high linearity and a superior S/N. In order to attenuate highfrequency noise caused by noise-shaping, internal low-pass filters are included. They require additional external capacitors between pins FILTR and OUTR, and FILTL and OUTL respectively (see Section 4.7. on page 81). Fig. 2-7: Bass/Treble Frequency Response 2.7.2. Micronas Dynamic Bass (MDB) 2.7.4. Output Amplifiers The Micronas Dynamic Bass system (MDB) was developed to extend the frequency range of loudspeakers or headphones below the cutoff frequency of the speakers. In addition to dynamically amplifying the low frequency bass signals, the MDB exploits the psychoacoustic phenomenon of the `missing fundamental'. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental, while at the same time retaining the loudness of the original signal. Due to the parametric implementation of the MDB, it can be customized to create different bass effects and adapted to various loudspeaker characteristics (see Section 3.4.4. on page 46). The integrated output amplifiers are capable of driving stereo headphones of 16...32 impedance via 22- series resistors or built-in loudspeakers of 16 impedance directly. If more output power is required, the right output signal can be inverted and a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this case the minimum impedance is 32 , and for optimized power the source should be set to mono. output level dBr -9 AVC off AVC on 2.7.2.1. Automatic Volume Correction (AVC) In a collection of tracks from different sources fairly often the average volume level varies. Especially in a noisy listening environment the user must adjust the volume to achieve a comfortable listening enjoyment. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see Table 3-17). For input levels of -18 dBr to 0 dBr, the AVC maintains a fixed output level of -9 dBr. Fig. 2-8 shows the AVC output level versus its input level. For volume and baseband registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. -15 -21 -30 -24 -18 -12 -6 +6 0 input level dBr Fig. 2-8: Simplified AVC characteristics MAS 3587F DAC DAC OUTL OUTR R 32 Fig. 2-9: Bridge operation mode 10 Micronas PRELIMINARY DATA SHEET MAS 3587F 2.8.1. DSP Clock The DSP clock has a separate divider. For power conservation it is set to the lowest acceptable rate of the synthesizer clock which is capable to allow the processor core to perform all tasks. 2.8. Clock Management The MAS 3587F is driven by a single crystal-controlled clock with a frequency of 18.432 MHz. It is possible to drive the MAS 3587F with other reference clocks. In this case, the nominal crystal frequency must be written into memory location D0:7F3. The crystal clock acts as a reference for the embedded synthesizer that generates the internal clock. For compressed audio data reception, the MAS 3587F may act either as the clock master (Demand Mode) or as a slave (Broadcast Mode) as defined by bit 1 in IOControlMain memory cell (see Table 3-9). In both modes, the output of the clock synthesizer depends on the sample rate of the decoded data stream as shown in Table 2-1. In the 'Broadcast Mode' (PLL on), the incoming audio data controls the clock synthesizer via a PLL. In the 'Demand Mode' (PLL off) the MAS 3587F acts as the system master clock, the internal clock. The data transfer is triggered by a demand signal at pin EOD. This mode is used in most applications. In the encoder application, the MAS 3587F is clock master in case of I2S audio input. For S/PDIF input, the MAS 3587F synchronizes the clock to the incoming S/PDIF signal. Table 2-1: Settings of bits 8 and 17 in OutClkConfig and resulting CLKO output frequencies Output Frequency at CLKO/MHz Synth. Scaler On Scaler Plus Clock bit 8=0, bit 17=0 Extra Division fs/kHz bit 8=1 bit 8=0, bit 17=1 48 44.1 32 24.576 24 22.05 16 24.576 12 11.025 22.5792 8 24.576 512fs 768fs 6.144 5.6448 6.144 256fs 384fs 3.072 2.8224 3.072 22.5792 512fs 768fs 12.288 11.2896 12.288 256fs 384fs 6.144 5.6448 6.144 24.576 22.5792 512fs 768fs 24.576 22.5792 24.576 256fs 384fs 12.288 11.2896 12.288 2.8.2. Clock Output at CLKO If the DSP or audio codec functions are enabled (bits 11 or 10 in the CONTROL Register at I2C subaddress 6Ahex), the reference clock at pin CLKO is derived from the synthesizer clock. Dependent on the sample rate of the decoded signal a scaler is applied which automatically divides the clockout by 1, 2, or 4, as shown in Table 2-1. An additional division by 2 may be selected by setting bit 17 of the Output Clock Configuration memory cell, OutClkConfig (see Table 3-9 on page 30). The scaler can be disabled by setting bit 8 of this cell. The controlling at OutClkConfig is only possible as long as the DSP is operational (bit 10 of the CONTROL Register). Settings remain valid if the DSP is disabled by clearing bit 10. 2.9. Power Supply Concept The MAS 3587F has been designed for minimal power dissipation. In order to optimize the battery management in portable players, two DC/DC converters have been implemented to supply the complete portable audio player with regulated voltages. 2.9.1. Power Supply Regions The MAS 3587F has five power supply regions. The VDD/VSS pin pair supplies all digital parts including the DSP core, the XVDD/XVSS pin pair is connected to the digital signal pin output buffers, the AVDD0/AVSS0 supply is for the analog output amplifiers, AVDD1/AVSS1 for all other analog circuits like clock oscillator, PLL circuits, system clock synthesizer and A/D and D/A converters. The I2C interface has an own supply region via pin I2CVDD. Connecting this to the microcontroller supply assures that the I2C bus always works as long as the microcontroller is alive so that the operating modes can be selected. Beside these regions, the DC/DC converters have start-up circuits of their own which get their power via pin VSENSx. Micronas 11 MAS 3587F 2.9.2. DC/DC Converters The MAS 3587F has two embedded high-performance step-up DC/DC converters with synchronous rectifiers to supply both the DSP core itself and external circuitry such as a controller or flash memory at two different voltage levels. An overview is given in Fig. 2-10 on page 13. The DC/DC converters are designed to generate an output voltage between 2.0 V and 3.5 V which can be programmed separately for each converter via the I2C interface (see Table 3-3 on page 20). Both converters are of the bootstrapped type which allow start up from a voltage down to 0.9 V for use with a single battery or NiCd/NiMH cell. The default output voltages are 3.0 V. Both converters are enabled with a high level at pin DCEN and enabled/disabled by the I2C interface. The MAS 3587F DC/DC converters feature a constant-frequency, low noise pulse width modulation (PWM) mode and a low quiescent current, pulse frequency modulation (PFM) mode for improved efficiencies at low current loads. Both modes - PWM or PFM - can be selected independently for each converter via I2C interface. The default mode is PWM. In the PWM mode, the switching frequency of the power-MOSFET-switches is derived from the crystal oscillator. Switching harmonics generated by constant frequency operation are consistent and predictable. When the audio codec is enabled the switching frequency of the converters is synchronized to the audio codec clock to avoid interferences into the audio band. The actual switching frequency can be selected via the I2C-interface between 300 kHz and 580 kHz (for details see DCFR Register in Table 3-3). In the PFM operation mode, the switching frequency is controlled by the converters themselves, it will be just high enough to service the output load thus resulting in the best possible efficiency at low current loads. PFM mode does not need a clock signal from the crystal oscillator. If both converters do not use the PWMmode, the crystal clock will be shut down as long it is not needed from other internal blocks. The synchronous rectifier bypasses the external Schottky diode to reduce losses caused by the diode forward voltage providing up to 5% efficiency improvement. By default, the P-channel synchronous rectifier switch is turned on when the voltage at pin(s) DCSOn exceeds the converter's output voltage at pin(s) VSENSn and turns off when the inductor current drops below a threshold. If one or both converters are disabled, the corresponding P-channel switch will be turned on, connecting the battery voltage to the DC/DC converters output voltage at pin VSENSn. PRELIMINARY DATA SHEET If both DC/DC-converters are off, a high signal may be applied at pin DCEN. This will start the converters in their default mode (PWM with 3.0 V output voltage). The PUP signal will change from low to high when both converters have reached their nominal output voltage and will return to low when both converters output voltages have dropped 200 mV below their programmed output voltage. The signal at pin PUP can be used to control the reset of an external microcontroller (see Section 2.13.2. on page 16 for details on start up procedure). If only DC/DC-converter 1 is used, the output of the unused converter 2 (VSENS2) must be connected to the output of converter 1 (VSENS1) to make the PUP signal work properly. Also, if a DC/DC-converter is not used (no inductor connected), the pin DCSO must be left vacant. 12 Micronas PRELIMINARY DATA SHEET MAS 3587F battery voltage monitor to I2C interface DCCF (76hex) 15 8 VBAT I2CVDD supply output 1 DCSO2 L1 22 H DC/DC converter 2 DCSG2 D1 VSENS2 set voltage voltage monitor DCEN S PUP Start + - C1 330 F PUP2 + - + - Vin system or crystal clock frequency divider factor 0 R 3 voltage monitor DCFR (77hex) DCCF (76hex) 7 0 DC/DC converter 1 VSS Fig. 2-10: DC/DC converter overview (DCEN input must be connected to pin I2CVDD via the start-up push button) Micronas 13 MAS 3587F 2.9.3. Power Supply Configurations One of the following supply configurations may be used: - Configuration 1: DC/DC 1 (e.g. 2.7 V) supplies controller, flash and MAS 3587F audio parts, DC/DC 2 generates e.g. 2.5 V/3.5 V for the MAS 3587F DSP (see Fig. 2-11). - Configuration 2: All components are powered by an external source, no DC/DC converter is used (see Fig. 2-12). - Configuration 3: The external source has a constant voltage of 2.7 V or 3 V, one DC/DC-converter is used to generate the higher DSP-Voltage needed for encoding (see Fig. 2-13) If DC/DC converter 1 is used, it must supply the analog circuits (pins AVDD0, AVDD1) of the MAS 3587F. If the DC/DC converters are not used, pin DCEN must be connected to VSS, DCSOx must be left vacant. VSENS1 PRELIMINARY DATA SHEET Flash DC/DC1 off C I2CVDD I2C DSP DC/DC2 off XVDD VDD VSENS2 External Supply AVDD0/1 e.g. 3.5 V/ 2.7 V Analog Parts Fig. 2-12: Configuration 2: External power supply 2.10. Battery Voltage Supervision A battery voltage supervision circuit (at pin VBAT) is provided which is independent of the DC/DC converters. It can be programmed to supervise one or two battery cells. The voltage is measured by subsequently setting a series of voltage thresholds and checking the respective comparison result in register 77hex (see Table 3-3). Flash VSENS1 DC/DC1 on C I2CVDD I 2C DSP DC/DC2 off XVDD VDD VSENS1 Flash DC/DC1 on VSENS2 C I2CVDD External Supply I2C DSP e.g. 2.7 V e.g. 3.5 V/ 2.7 V AVDD0/1 Analog Parts XVDD VDD VSENS2 DC/DC2 on Fig. 2-13: Configuration 3: External constant power supply AVDD0/1 e.g. 2.7 V e.g. 3.5 V /2.5 V Analog Parts Fig. 2-11: Configuration1: DC/DC-converter supply 14 Micronas PRELIMINARY DATA SHEET MAS 3587F 2.11.4. Multiline Serial Audio Input (SDI, SDIB) There are two multiline serial audio input interfaces (SDI, SDIB) each consisting of the three pins SIC, SII, SID, and SIBC, SIBI, SIBD. The firmware supports SDI for audio signals and SDIB for bitstream signals. The interfaces can be configured as continuous bit stream or word-oriented inputs. For the MPEG bitstreams the word strobe pin SIBI must always be connected to VSS, bits must be sent MSB first as created by the encoder. During enabling the DSP and its interfaces, it is strongly recommended to hold the SIBC Pin low. In case of the Demand Mode in decoding applications (see Section 2.8.), the signal clock coming from the data source must be higher than the nominal data transmission rate (e.g. 128 kbit/s). Pin EOD is used to interrupt the data flow whenever the input buffer of the MAS 3587F is filled. For controlling details please refer to Table 3-9. 2.11. Interfaces The MAS 3587F uses an I2C control interface, a parallel I/O interface (PIO) for MPEG bit streams and digital audio interfaces for the incoming/outgoing audio data (I2S or similar). Alternatively, SPDIF input and output interfaces can be used. MPEG bit stream input to the decoder is also possible via a second serial input interface. 2.11.1. I2C Control Interface For controlling and program download purposes, a standard I2C slave interface is implemented. A detailed description of all functions can be found in Section 3. 2.11.2. S/PDIF Input Interface The S/PDIF interface receives a one-wire serial bus signal. In addition to the signal input pin SPDI1/SPDI2, a reference pin SPDIR is provided to support balanced signal sources or twisted pair transmission lines. The synchronization time on the input signal is < 50 ms. The S/PDIF input signal can also be switched to the SPDO pin. In this case the analog input circuit of the S/PDIF inputs (see Fig. 4-18 on page 55) restores the S/PDIF input signal to a full swing signal at SPDO. For controlling details please refer to Table 3-9 on page 30. 2.11.5. Multiline Serial Output (SDO) The serial audio output interface of the MAS 3587F is a standard I2S-like interface consisting of the data lines SOD, the word strobe SOI and the clock signal SOC. It is possible to choose between two standard interface configurations (16-bit data words with word strobe time offset or 32-bit data words with inverted SOI-signal). If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default. 2.11.3. S/PDIF Output The S/PDIF output of the baseband audio signals is provided at pin SPDO. Note that the S/PDIF output is available only for MPEG 1 sampling frequencies (32, 44.1, 48 kHz). 2.11.6. Parallel Input/Output Interface (PIO) The parallel interface of the MAS 3587F consists of the 8 data lines PI12...PI19 (MSB) and the control lines PCS, PR, PRTR, PRTW, and EOD. It can be used for data exchange with an external memory and for other special purposes as defined by the DSP software. The PIO interface is always used for MPEG-data output. For the handshake protocol please refer to Section 4.6.3.8. For MPEG-data input, the PIO interface is activated by setting bits 9,8 in D0:7F1 to 01. For the handshake protocol please refer to Section 4.6.3.6. Micronas 15 MAS 3587F 2.12. MPEG Synchronization Output The signal at pin SYNC is set to `1' after the internal decoding for the MPEG header has been finished for one frame. The rising edge of this signal can be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. As soon as the MAS 3587F has received the SYNC reset command (see Section 3.3.2.8. on page 26), the SYNC signal is cleared. If the controller does not issue a reset command, the SYNC signal returns to '0' as soon as the decoding of the next MPEG frame is started. MPEG status and ancillary data become invalid until the frame is completely decoded and the signal at pin SYNC rises again. The controller must have finished reading all MPEG information before it becomes invalid. The MPEG Layer 2/3 frame lengths are given in Table 2-2. PRELIMINARY DATA SHEET 2.13. Default Operation This sections refers to the standard operation mode "Configuration 1" (see Section 2.9.3.). 2.13.1. Stand-by Functions After applying the battery voltage, the system will remain stand-by, as long as the DCEN pin level is kept low. Due to the low stand-by current of CMOS circuits, the battery may remain connected to DCSOn/VSENSn at all times. 2.13.2. Power-Up of the DC/DC Converters and Reset The battery voltage must be applied to pin DCSOn via the 22 H inductor and, furthermore, to the sense pin VSENSn via a Schottky diode (see Fig. 2-10 on page 13). tframe = 24...72 ms Vh Vl tread Fig. 2-14: Schematic timing of the signal at pin SYNC. The signal is cleared at tread when the controller has issued a Clear SYNC Signal command (see Section 3.3.2.8. on page 26). If no command is issued, the signal returns to '0' just before the decoding of the next MPEG frame. Table 2-2: Frame length in MPEG Layer 2/3 fs/kHz 48 44.1 32 24 22.05 16 12 11.025 8 Frame Length Layer 2 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms not available not available not available Frame Length Layer 3 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms 48 ms 52.24 ms 72 ms For start-up, the pin DCEN must be connected via an external "start" push button to the I2CVDD supply, which is equivalent to the battery supply voltage (> 0.9 V) at start-up. The supply at DCEN must be applied until the DC/DC converters have started up (signal at pin PUP) and then removed for normal operation. As soon as the output voltage at VSENSn reaches the default voltage monitor reset level of 3.0 V, the respective internal PUPn bit will be set. When both PUPn bits are set, the signal at pin PUP will go high and can be used to start and reset the microcontroller. Before transmitting any I2C commands, the controller must issue a power-on reset to pin POR. The separate supply pin I2CVDD assures that the I2C interface works independently of the DSP or the audio codec. Now the desired supply voltage can be programmed at I2C subaddress 76hex (see Table 3-3). The signal at pin PUP will return to low only when both PUPn flags (I2C subaddress 76hex) have returned to zero. Care must be taken when changing both DC/DC output voltages to higher values. In this case, both output voltages are momentarily insufficient to keep the PUPn flags up; the resulting dip in the signal at the PUP pin may in turn reset the microcontroller. To avoid this condition, only one DC/DC output voltage should be changed at a time. Before modifying the second voltage, the microcontroller must wait for the PUPn flag of the first voltage to be set again. If only DC/DC converter 1 is used, the reference voltage of the second unused should be set to a lower value than that of converter 1 and its pin VSENS2 should be connected to VDD. 16 Micronas PRELIMINARY DATA SHEET MAS 3587F 2.13.4. Start-up of the Audio Codec Before enabling the audio codec, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The audio codec is enabled by setting the appropriate bit at the CONTROL register (I2C subaddress 6Ahex). After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C. The A/D and the D/A converters must be switched on explicitly (00 00hex at I2C subaddress 6chex). The D/A converters may either accept data from the A/D converters or the output of the DSP, or a mix of both (register 00 06hex and 00 07hex at I2C subaddress 6Chex). Finally, an appropriate output volume (00 10hex at I2C subaddress 6Chex) must be selected. The operating mode (pulse width modulation or pulse frequency modulation) are controlled at I2C subaddress 76hex, the operating frequency at I2C subaddress 77hex. 2.13.3. Control of the Signal Processing Before starting the DSP, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The DSP is enabled by setting the appropriate bit in the CONTROL register (I2C subaddress 6Ahex). The nominal frequency of the crystal oscillator must be written into D0:7F3. After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C (see Table 3-3). Input and output control is performed via memory location D0:7F1 and D0:7F2. The parallel interface (PIO) is the default setting for compressed data. The decoded audio can be routed to either the S/PDIF, the SDO and the analog outputs. The output clock signal at pin CLKO is defined in D0:7F4. The specific settings for audio encoding are written to memory location D0:7F0. All changes in the D0-memory cells become effective synchronously upon setting the LSB of Main I/O Control D0:7F1 (see Table 3-9). The common way to start encoding or decoding is to perform all necessary settings and switch on the application by selecting the desired bit(s) in the Application Selection memory cell (D0:7F6) (see Table 3-9). The digital volume control (see Table 3-9) is applied to the output signal of the DSP. The decoded audio data is by default available at the S/PDIF output interface (for MPEG 1 sampling frequencies). The DSP does not have to be started if its functions are not needed, e.g. for routing audio via the A/D and the D/A converters through the codec part of the IC. 2.13.5. Power-Down All analog outputs should be muted and the A/D and the D/A converters must be switched off (register 00 10hex and 00 00hex at I2C subaddress 6Chex). The DSP and the audio codec must be disabled (clear DSP_EN and CODEC_EN bits in the CONTROL register, I2C subaddress 6Ahex). By clearing both DC/DC enable flags in the CONTROL register (I2C subaddress 6Ahex), the microcontroller can power down the complete system. Micronas 17 MAS 3587F 3. Controlling 3.1. I2C Interface Controlling between the MAS 3587F and the external controller is done via an I2C slave interface. PRELIMINARY DATA SHEET Table 3-2: I2C Subaddresses Subaddress (hex) I2CRegister Name Function Direct Configuration 3.1.1. Device Address The device addresses are 3C/3Ehex (device write "DW") and 3D/3Fhex (device read, "DR") as shown in Table 3-1. The device address pair 3C/3Dhex applies if the DVS pin is connected to VSS, the device address pair 3E/3Fhex applies if the DVS pin is connected to I2CVDD. Table 3-1: I C device address A7 0 A6 0 A5 1 A4 1 A3 1 A2 1 A1 DVS W/R 0/1 DSP Core Access 68 69 data_write data_read Controller writes to MAS 3587F DSP Controller reads from MAS 3587F DSP 2 6A CONTROL Controller writes to MAS 3587F CONTROL register Controller writes to first DC/DC configuration register Controller writes to second DC/DC configuration register 76 DCCF 77 DCFR I2C clock synchronization is used to slow down the interface if required. 3.1.2. I2C Registers and Subaddresses The interface uses one level of subaddresses. The MAS 3587F interface has 7 subaddresses allocated for the corresponding I2C registers. The registers can be divided into three categories as shown in Table 3- 2. The address 6Ahex is used for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 3587F. The I2C registers of the MAS 3587F are 16 bits wide, the MSB is denoted as bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus, for each register access, two 8-bit data words must be sent/received via I2C bus. Codec Access 6C codec_write Controller writes to MAS 3587F codec register Controller reads from MAS 3587F codec register 6D codec_read 18 Micronas PRELIMINARY DATA SHEET MAS 3587F - Bus signals S Start P Stop A ACK = Acknowledge N NAK = Not acknowledge W Wait = I2C clock line is held low while the MAS 3587F is processing the current I2C command - Symbols in the telegram examples < Start Condition > Stop dd data bytes xx ignore All telegram numbers are hexadecimal, data originating from the MAS 3587F are greyed. Example: 3.1.3. Naming Convention The description of the various controller commands uses the following formalism: - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - Memory addresses like D1:89F are always in hexadecimal notation. - A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. - Data values in nibbles are always shown in hexadecimal notation. - A hexadecimal 20-bit number d is written, e.g. as d = 17C63hex, its five nibbles are d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and d4 = 1hex. - Variables used in the following descriptions: IC address: DW 3C/3Ehex I2C device write I2C device read DR 3D/3Fhex DSP core: data_write 68hex DSP data write DSP data read data_read 69hex Codec: codec_write 6Chex codec write codec read codec_read 6Dhex Example: I2C write access S DW W A subaddress A high byte data A low byte data W A P Example: I2C read access S DW W A subaddress A S DR A W A W N P high byte data low byte data SDA SCL S 1 0 P W = Wait A = Acknowledge (Ack) N = Not Acknowledge (NAK) S = Start P = Stop Fig. 3-1: Example of an I2C bus protocol for the MAS 3587F (MSB first; data must be stable while clock is high) Micronas 19 MAS 3587F 3.2. Direct Configuration Registers The task selection of the DSP and the DC/DC converters are controlled in the direct configuration registers CONTROL, DCCF, and DCFR. PRELIMINARY DATA SHEET 3.2.2. Read Direct Configuration Register S DW W A subaddr. A S d3,d2 DR A W A N P d1,d0 3.2.1. Write Direct Configuration Registers To check the PUP1 and PUP2 power-up flags, it is necessary to read back the content of the direct configuration registers. P S DW W A subaddr. A d3,d2 A d1,d0 A The write protocol for the direct configuration registers only consists of device address, subaddress and one 16-bit data word. Table 3-3: Direct Configuration Registers I2C Subaddress (hex) 6A Function Name Control Register (reset value = 3000hex) bit[15:14] Analog supply voltage range Code 00 01 10 11 AGNDC 1.1 V 1.3 V 1.6 V reserved recommended for voltage range of AVDD 2.0 ... 2.4 V (reset) 2.4 ... 3.0 V 3.0 ... 3.6 V reserved CONTROL Higher voltage ranges permit higher output levels and thus a better signal-tonoise ratio. bit[13] bit[12] Enable DC/DC 2 (reset = 1) Enable DC/DC 1 (reset = 1) Both DC/DC converters are switched on by default with DCEN = high (1). bit[11] bit[10] Enable and reset audio codec Enable and reset DSP core For normal operation (MPEG-decoding and D/A conversion), both, the DSP core and the audio codec have to be enabled after the power-up procedure. The DSP can be left off if an audio signal is routed from the analog inputs to the analog outputs (set bit[15] in codec register 00 0Fhex). The audio codec can be left off if the DSP uses digital inputs and outputs only. bit[9] bit[8] bit[7] bit[6:0] 1) Reset codec Reset DSP core Enable crystal input clock divider of 1.5 (extended range up to 28 MHz)1) Reserved, must be set to zero refer to Table 4-2 on page 58 20 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-3: Direct Configuration Registers, continued I2C Subaddress (hex) 76 Function Name DCCF Register (reset = 5050hex) DC/DC Converter 2 bit[15] bit[14:11] PUP2: Voltage monitor 2 flag (readback) Converter 2 output voltage with respect to VREF Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 01001) 00111) 00101) bit[10] Mode 1 0 Nominal output volt. 3.5 V 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V set level of PUP2 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V reset level of PUP2 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V (reset) 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V DCCF pulse frequency modulation (PFM) pulse width modulation (PWM) (reset) bit[9:8] Reserved, must be set to zero The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. 1) refer to Section 4.6.2. on page 57 DC/DC Converter 1 bit[7] bit[6:3] bit[2] PUP1: Voltage monitor 1 flag (readback) Converter 1 output voltage at VSENS1 with respect to VREF (see bits 14 to 11) Mode 1 0 pulse frequency modulation (PFM) pulse width modulation (PWM) (reset) bit[1:0] Reserved, must be set to zero Note, that the reference voltage for DC/DC converter 1 is derived from the main reference source supplied via pin AVDD1. Therefore, if this DC/DC converter is used, its output must be connected to the analog supply. The DC/DC converters are up-converters only. Thus, if the battery voltage is higher than the selected nominal voltage, the output voltage will exceed the nominal voltage. Micronas 21 MAS 3587F Table 3-3: Direct Configuration Registers, continued I2C Subaddress (hex) 77 Function PRELIMINARY DATA SHEET Name DCFR Register (reset = 00hex) Battery Voltage Monitor bit[15] Comparison result (readback) 1 input voltage at pin VBAT above defined threshold 0 input voltage at pin VBAT below defined threshold Number of battery cells 0 1 cell (range 0.8...1.5 V) (reset) 1 2 cells (range 1.6...3.0 V) Voltage threshold level 1 cell 2 cells 1111 1.5 3.0 V 1110 1.45 2.9 V ... 0010 0.85 1.7 V 0001 0.8 1.6 V 0000 battery voltage supervision off (reset) Reserved, must be set to 0 DCFR bit[14] bit[13:10] bit[9:8] The result is stable 1 ms after enabling. The setup time for switching between two thresholds is negligibly small. For power management reasons, the battery voltage monitor should be switched off by setting bit[13:10] to zero when the measurement is completed. DC/DC Converter Frequency Control (PWM) bit[7:4] bit[3:0] Reserved, must be set to 0 Frequency of DC/DC converter Reference: 24.576 0111 315.1 0110 323.4 0101 332.1 0100 341.3 0011 351.1 0010 361.4 0001 372.4 0000 384.0 1111 396.4 1110 409.6 1101 423.7 1100 438.9 1011 455.1 1010 472.6 1001 491.5 1000 512.0 22.5792 289.5 297.1 305.1 313.6 322.6 332.0 342.1 352.8 364.2 376.3 389.3 403.2 418.1 434.2 451.6 470.4 18.432 MHz 297.3 kHz 307.2 kHz 317.8 kHz 329.1 kHz 341.3 kHz 354.5 kHz 368.6 kHz 384.0 kHz (reset) 400.7 kHz 418.9 kHz 438.9 kHz 460.8 kHz 485.1 kHz 512.0 kHz 542.1 kHz 576.0 kHz If the audio codec is not enabled (bit 11 of the CONTROL register at I2C-subaddress 6Ahex is zero), the clock for the DC/DC converters is directly derived from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer clock is used as the reference (please refer to the respective column in Table 2-1 on page 11). 22 Micronas PRELIMINARY DATA SHEET MAS 3587F The MAS 3587F firmware scans the I2C interface periodically and checks for pending or new commands. The commands are then executed by the DSP during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. However, due to some time critical firmware parts, a certain latency time for the response has to be expected at the locations marked with a "W" (= wait). The theoretical worst case response time does not exceed 4 ms. However, the typical response time is less than 0.5 ms. Due to the 16-bit width of the I2C data register, all actions transmit telegrams with multiples of 16 data bits. 3.3. DSP Core 3.3.1. Access Protocol The I2C data register is used to communicate with the internal firmware of the MAS 3506D. It is readable (subaddress "data_read") and writable (subaddress "data_write") and also has a length of 16 bits. The data transfer is done with the most significant bit (m) first. Table 3-4: Data register bit assignment 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 m l A special command language is used that allows the controller to access the DSP-registers and RAM-cells and thus monitor internal states, set the parameters for the DSP-firmware, control the hardware, and even provide a download of alternative software modules. The DSP-commands consist of a "Code" which is sent to I2C-data register together with additional parameters. 3.3.2. Data Formats The internal data word size is 20 bits. All RAMaddresses can be accessed in a 20-bit mode via I2Cbus. Because of the 16-bit width of the I2C-data register the full transfer of all 20 bits requires two 16-bit I2Cwords. Some commands only access the lower 16 bits of a cell. For fast access of internal DSP-states the processor core also has an address space of 256 data registers. The internal data format is a 20 bit two's complement denoted "r". If in some cases a fixed point notation "v" is necessary. The conversion between the two forms of notation is done as follows: r = v*524288.0+0.5; (-1.0 v < 1.0) v = r/524288.0; (-524288 < r < 524287) S DW W A data_write A Code,... A ...,... A ... Fig. 3-2: General core access protocol Table 3-5 on page 24 gives an overview over the different commands which the DSP Core receives via the I2C data register. The "Code" is always the first data nibble transmitted after the "data_write" subaddress byte. A second auxiliary code nibble is used for the short memory (16-bit) access commands. Micronas 23 MAS 3587F Table 3-5: Basic controller command codes Code (hex) 0...3 5 6 7 A B C D E F Command Run Read Ancillary Data Fast Program Download Read IC Version Read from Register Write to Register Read D0 Memory Read D1 Memory Write D0 Memory Write D1 Memory Function PRELIMINARY DATA SHEET Start execution of an internal program. Run with start address 0 means freeze the operating system. The controller reads a block of MPEG Ancillary Data from the MAS 3587F The controller downloads custom software via the PIO interface The controller reads the version information of the IC The controller reads an internal register of the MAS 3587F The controller writes an internal register of the MAS 3587F The controller reads a block of the DSP memory The controller reads a block of the DSP memory The controller writes a block of the DSP memory The controller writes a block of the DSP memory 3.3.2.1. Run and Freeze (Codes 0hex to 3hex) S DW W A data_write A a3,a2 A a1,a0 W A P The Run command causes the start of a program part at address a = (a3,a2,a1,a0). Since nibble a3 is also the command code (see Table 3-5), it is restricted to values between 0 and 3. This command is used to start alternate code or downloaded code from a RAMarea that has been configured as program RAM. If the start address is 1000hex a < 3FFFhex and the respective RAM area has been configured as program RAM (see Table 3-7 on page 28), the MAS 3587F continues execution with a custom program already downloaded to this area. Example 1: Start program execution at address 345hex: Freeze is a special run command with start address 0. It suspends all normal program execution. The operating system will enter an idle loop so that all registers and memory cells can be watched. This state is useful for operations like downloading code or contents of memory cells because the internal program cannot overwrite these values. This freezing will be required if alternative software is downloaded into the internal RAM of the MAS 3587F. Freeze has the following I2C protocol: 24 Micronas PRELIMINARY DATA SHEET MAS 3587F 3.3.2.2. Read Register (Code Ahex) 1) send command (Read D0) 1) send command S DW W A data_write A A,r1 A r0,0 W A P S DW W A data_write A C,0 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 2) get register value S DW x,x W A A data_read A x,d4 W A S d3,d2 DR A W A W N P 2) get register value S DW x,x W A A data_read A x,d4 W A S d3,d2 DR A W A W A d1,d0 d1,d0 ....repeat for n data values.... The MAS 3587F has an address space of 256 DSPregisters. Some of the registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. In Table 3-7, the registers of interest are described in detail. In contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. Example: Read the content of register C8hex: x,x A x,d4 W A d3,d2 A d1,d0 W N P The Read D0 Memory command gives the controller access to all 20 bits of the D0/D1 memory cells. The telegram to read 3 words starting at location D1:100 is 3.3.2.5. Short Read Memory (Codes C4hex and D4hex) Because most cells in the user interface are only 16 bits wide, it is faster and more convenient to access the memory locations with a special 16 bit mode for reading: 3.3.2.3. Write Register (Code Bhex) S DW W A data_write A B,r1 d3,d2 A A r0,d4 d1,d0 W W A A P 1) send command (e.g. Short Read D0) S DW W A data_write A C,4 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P The controller writes the 20-bit value (d = d4,d3,d2, d1,d0) into the MAS 3587F register (r = r1,r0). A list of registers needed for control purposes is given in Table 3-7. Example: Writing the value 81234hex into the register with the number AAhex: 2) get register value S DW W A data_read A S d3,d2 DR A W A W A d1,d0 ....repeat for n data values.... d3,d2 A d1,d0 W N P 3.3.2.4. Read Memory (Codes Chex and Dhex) The MAS 3587F has 2 memory areas of 2048 words denoted D0 and D1 . The memory areas D0 and D1 can be written by using the codes Chex and Dhex, respectively. This command is similar to the normal 20 bit read command and uses the same command code Chex and Dhex for D0 and D1-memory, respectively, however it is followed by a 4hex rather than a 0hex. Example: Read 16 bits of D1:123 has the following I2C protocol: Micronas 25 MAS 3587F 3.3.2.6. Write Memory (Codes Ehex and Fhex) The memory areas D0 and D1 can be written by using the codes Ehex and Fhex, respectively. 3.3.2.9. Default Read PRELIMINARY DATA SHEET The Default Read command is the fastest way to get information from the MAS 3587F. Executing the Default Read in a polling loop can be used to detect a special state during decoding. S DW W A data_write A E,0 n3,n2 a3,a2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A S DW W A data_read A S DR d3,d2 W A A d1,d0 W N P x,x A x,d4 W A d3,d2 ....repeat for n data values.... x,x A x,d4 W A d3,d2 A d1,d0 W A P With the Write D0/D1 Memory command n 20-bit memory cells in D0 can be initialized with new data. Example: Write 80234hex to D1:456 has the following I2C protocol: <3a 68 f0 00 00 01 04 56 00 08 02 34> write D1 memory 1 word to write start address value = 80234hex The Default Read command immediately returns the lower 16 bit content of a specific RAM location as defined by the pointer D0:FFB. The pointer must be loaded before the first Default Read action occurs. If the MSB of the pointer is set, it points to a memory location in D1 rather than to one in D0. Example: For watching D1:123 the pointer D0:FFB must be loaded with 8123hex: 3.3.2.7. Short Write Memory (Codes E4hex and F4hex) Now the Default Read commands can be issued as often as desired: Default Read command 16 bit content of the address as defined by the pointer S DW W A data_write A A A A E,4 n3,n2 a3,a2 d3,d2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A ....repeat for n data values.... A d3,d2 A d1,d0 W A P For faster access only the lower 16 bits of each memory cell are written. The 4 MSBs of the cell are cleared. The command uses the same codes Ehex and Fhex for D0/D1 as for the 20-bit command but followed by a 4 rather than a 0. S DW W A data_write A 6,n2 a3,a2 A A n1,n0 a1,a0 W W A A P 3.3.2.8. Clear SYNC Signal (Code 5hex) S DW W A data_write A 5,0 A 0,0 W A P The Fast Program Download command introduces a data transfer via the parallel port. n = n2,n1,n0 denotes the number of 20-bit data words to be transferred, a = a3,a2,a1,a0 gives the start address. The data must be organized in two times five nibbles to get two words of 20-bit length. If the number n of 20-bit data words is odd, the very last word has to be padded with one additional nibble. After a successful decoding of an MPEG frame the signal at pin SYNC rises and thus generates an interrupt event for the microcontroller. Issuing this command lets the signal at pin SYNC return to '0'. 26 Micronas PRELIMINARY DATA SHEET MAS 3587F 3.3.2.11. Serial Program Download Program downloads may also be performed via the I2C-interface by using the Write D0/D1 Memory commands. A similar command sequence as in the Fast Program Download (Freeze, stop transfers...) applies. The download must be initiated in the following order: - Issue Freeze command - Stop all DMA-transfers - Issue Fast Program Download command - Download code via PIO-interface - Switch appropriate memory area to act as program RAM (register edhex) - Issue a Run command to start program execution at entry point of downloaded code Example for Fast Program Download command: Download 5 words starting at D0:800, then download 4 words starting at D1:200: 3.3.2.12. Read IC Version (Code 7hex) 1) send command S DW W A data_write A 7,0 A 0,0 W A P 2) get version information S DW W A data_read A S n3,n2 d3,d2 DR A A W A W W A N P n1,n0 d1,d0 With this command the version of the IC is read in two 16 bit words. The first word n = n3,n2,n1,n0 contains the IC's major number (one nibble for each digit). The second word (d = d3,d2,d1,d0) returns the version as shown in Table 3-6. Table 3-6: Second word of version information Bit 15:12 11:8 Nibble d3 d2 Content IC family derivate Coded character of order version (add 41hex to the content of d2 to get ASCII) Digit of order version Now transfer 5 20-bit words via the parallel PIO-port: d4,d3 d4,d3 d4,d3 d2,d1 d2,d1 d2,d1 d0,d4 d0,d4 d0,x d3,d2 d3,d2 d1,d0 d1,d0 initiate download of 4 words start at address D1:200 7:0 d1,d0 Now transfer 4 20-bit words via the parallel PIO-port: d4,d3 d4,d3 d2,d1 d2,d1 d0,d4 d0,d4 d3,d2 d3,d2 d1,d0 d1,d0 Example: Read the version information for MAS 3587F, derivate 0, order version B2: Micronas 27 MAS 3587F 3.3.3. List of DSP Registers Table 3-7 lists the registers used in the standard firmware (MPEG) and for the download option (Download). Note: Registers not given in the tables must not be written. PRELIMINARY DATA SHEET 3.3.4.1. Application Selection and Application Running The AppSelect cell is a global user interface configuration cell which has to be written in order to start a specific application. The AppRunning cell is a global user interface status cell, which indicates, which application loop is actually running. Following steps have to be performed to switch between applications: 1. Write "0" to AppSelect 2. Check AppRunning for "0" 3. For encoder (version B2 only): - write 98hex to register a3hex - write FFFFFhex to register 94hex - write 0 to D1:000 - write 90hex to register A3hex 4. Apply necessary/wanted control settings (D0: 7F0..7FF) 5. Write value to AppSelect according to Table 3-8 (determines start time of Application program) 3.3.4. List of DSP Memory Cells Among the user interface control memory cells there are some which have a global meaning and some which control application specific parts of the DSP core. In the tables below this is reflected by the mode keywords All, Encoder and Decoder. The operation mode is chosen in the AppSelect cell. Table 3-7: DSP Register Table Address (hex) 6B R/W R/W Function Configuration of Variable RAM Areas bit[19] bit[18] bit[17] bit[16] Affected RAM area D0:800 ... D0:BFF D0:c00 ... D0:FFF D1:800 ... D1:BFF D1:c00 ... D1:FFF Mode Download Default (hex) 0000 Name PSelect_Shadow This register is used to switch four RAM areas from data to program usage and thus enabling the DSP's program counter to access downloaded program code stored at these locations. For normal operation (firmware in ROM) this register must be kept to zero. For details of program code download please refer to Section 3.3.2.10. on page 26 56 R S/PDIF1) Input Channel Status Bits bit[15:0] 1) MPEG 0000 SPIChannelStatus channel status bits of incoming signal. IEC 958 Amendment1, "Digital Audio Interface" 28 Micronas PRELIMINARY DATA SHEET MAS 3587F The status memory cells are used to read the encoder/ decoder status and to get additional MPEG bitstream information. Note: Memory cells not given in the tables must not be written. 3.3.4.2. Application Specific Control The configuration of the MPEG encoder and decoder firmware is done via the control memory cells described in Table 3-9. The changes applied to any of the control memory cells have to be validated by setting bit[0] of memory cell Main I/O Control except when the application is started by writing the AppSelect memory cell. The validate bit will be reset automatically after the changes have been taken over by the DSP. Table 3-8: D0 Memory Cells: Mode Selection Memory Address (hex) D0:7F6 Function Mode Name Application Selection All AppSelect AppSelect is used for selecting an application. This is done by setting the appropriate bit to one. It is principally allowed to set more than one bit to one, e.g. setting AppSelect to 0Chex will select all MPEG audio decoders. The auto-detection feature will automatically detect the Layer 2 or Layer 3 data. When bit[0]/bit[1] are asserted, the DSP begins to loop inside the OS loop/Top Level loop respectively. It is recommended to perform the necessary settings for the firmware before the application is started by writing this memory cell. bit[19:7] bit[5:4] bit[6] bit[3] bit[2] bit[1:0] D0:7F7 Reserved, must be set to zero Reserved, must be set to zero MPEG Layer 3 Encoder MPEG Layer 3 Decoder MPEG Layer 2 Decoder Reserved, must be set to zero All AppRunning Application Running The AppRunning cell is a global user interface status cell, that indicates which application loop is actually running. After writing AppSelect, it has to be checked whether the appropriate bit(s) in the AppRunning cell is set, prior to any changes in the configuration registers or memory cells. bit[19:7] bit[5:4] bit[6] bit[3] bit[2] bit[1:0] Reserved, must be set to zero Reserved, must be set to zero MPEG Layer 3 Encoder MPEG Layer 3 Decoder MPEG Layer 2 Decoder Reserved, must be set to zero Micronas 29 MAS 3587F Table 3-9: D0 Control Memory Cells Memory Address (hex) D0:7F01) Function PRELIMINARY DATA SHEET Mode Name Encoder Control (reset = A0264hex) Encoder EncoderControl EncoderControl is used for selecting the quality level, sample frequency and other options for encoding. bit[19:17] Quality Setting (see Section 3.3.7.1. on page 39) 000 0 lowest bitrate/quality 001 1 010 2 011 3 100 4 101 (reset) 5 recommended quality 110 6 111 7 highest bitrate/quality Reserved, must be set to zero Sampling Frequency (kHz) 00 (reset) 01 10 11 MPEG 1 44.1 48 32 reserved MPEG 2 22.05 24 16 bit[16:12] bit[11:10] bit[9] MPEG Selection 0 MPEG 2 1 (reset) MPEG 1 Note that the clock frequency (bit[3] in D0:7F1) must be set accordingly. Bit[11:9] are only evaluated for SDI audio input (selected in D0:7F11), bit[9:8]). In case of S/PDIF audio input, MPEG 1 is used and the sampling frequency is auto detected. bit[8] CRC protection 0 (reset) enable CRC protection 1 disable CRC protection Channel Mode 00 reserved 01 (reset) joint stereo 10 reserved 11 single channel Channel Mode Extension (for joint stereo) 0 disable MS-Stereo encoding 1 (reset) enable MS-Stereo encoding Reserved, must be set to zero Copyright 0 (reset) 1 (see Section 3.3.5. on page 37) bit stream is not copyright protected bit stream is copyright protected bit[7:6] bit[5] bit[4] bit[3] bit[2] Copy/Original (see Section 3.3.5. on page 37) 0 bit stream is a copy 1 (reset) bit stream is an original Emphasis 00 (reset) 01 10 11 none 50/15 s reserved CCITT J.17 bit[1:0] 30 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-9: D0 Control Memory Cells, continued Memory Address (hex) D0:7F11) Function Mode Name Main I/O Control (reset = 125hex) All IOControlMain IOControlMain is used for selecting/deselecting the appropriate data input interface and for setting up the serial data output interface. In serial input mode the coded audio data (Layer 2, Layer 3) is expected at the serial input interface SDIB. In the 8-bit-parallel input mode (default) the PIO pins PI[19:12] are used. bit[15] bit[14] Reserved, must be set to zero Invert serial output clock (SOC) 0 (reset) do not invert SOC 1 invert SOC Reserved, must be set to zero Encoder: Add timecode to encoded bitstream 0 (reset) no timecode is inserted 1 insert timecode into ancillary data bits bit[13] bit[12] The format of the timecode is explained in Section 3.3.7.1. on page 39 bit[11] Serial data output delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe Encoder: Low power loop-through mode 0 (reset) normal encoder operation 1 audio data loop-through without encoding bit[10] The low power loop-through mode is for monitoring audio signals without encoding and data transfer to the PIO interface. It is controlled just like in normal encoding mode (audio input/MPEG mode selection), but power consumption and voltage requirements are as in decoding mode. bit[9:8] Encoder: Audio input select 00 SDI input with PLL 01 (reset) SDI input without PLL 10 S/PDIF input 11 reserved Decoder: Data input select 00 serial input at interface B 01 (reset) parallel input at PIO pins PI[19...12] 10 reserved 11 reserved bit[7] Encoder: Invert serial input clock (SIC) 0 (reset) do not invert SIC 1 invert SIC Encoder: Serial data input delay 0 (reset) no additional delay (reset) 1 additional delay of data related to word strobe SDO Word strobe invert 0 do not invert 1 (reset) invert outgoing word strobe signal bit[6] bit[5] ... 1) Changes at this memory address must be validated by setting bit[0] of D0:7F11). Micronas 31 MAS 3587F Table 3-9: D0 Control Memory Cells, continued Memory Address (hex) D0:7F1 (continued) Function PRELIMINARY DATA SHEET Mode Name Main I/O Control (continued) bit[4] Bits per sample at SDO 0 (reset) 32 bits/sample 1 16 bits/sample Encoder: Clock setting 0 (reset) MPEG 1 1 MPEG 2 bit[3] Please note the supply voltage restrictions for MPEG 1. bit[2] Decoder: Serial data input interface B clock invert (pin SIBC) 0 not inverted (data latched at rising clock edge) 1 (reset) incoming clock signal is inverted (data latched at falling clock edge) Encoder: SDI word strobe invert 0 do not invert 1 (reset) invert incoming word strobe signal Decoder: 0 (reset) 1 bit[0] Validate 0 (reset) 1 DEMAND MODE (PLL off, MAS 3587F is clock master) BROADCAST MODE (PLL on, clock of MAS 3587F locks on data stream) bit[1] changes in control memory will become effective Bit[0] is reset after the DSP has recognized the changes. The controller should set this bit after the other D0 control memory cells have been initialized with the desired values. 32 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-9: D0 Control Memory Cells, continued Memory Address (hex) D0:7F21) Function Mode Name Interface Status Control (reset = 05hex) All InterfaceControl This control cell allows to enable/disable the data I/O interfaces. In addition, the clock of the output data interfaces, S/PDIF and SDO, can be set to a low-impedance mode. bit[6] S/PDIF input selection 0 (reset) select S/PDIF input 1 1 select S/PDIF input 2 Enable/disable S/PDIF output 0 (reset) enable S/PDIF output 1 S/PDIF output invalid bit[5] Note that S/PDIF audio output is only available for MPEG 1 (sampling frequencies 32, 44.1, and 48 kHz) bit[4] bit[3] Reserved, must be set to zero Enable/disable serial data output SDO 0 (reset) SDO valid data 1 SDO invalid data Output clock characteristic (SDO and S/PDIF outputs) 0 low impedance 1 (reset) high impedance reserved, must be set to zero Enable/disable external serial data input SDI2) 0 use external audio source (SDI) 1 (reset) use internal A/D converter as audio source bit[2] bit[1] bit[0] For details regarding the SDI-interface please see the MAS 3587F Application Note. Both digital outputs, S/PDIF and SDO, and the D/A converters may use the outgoing audio independent of each other. D0:7F31) Oscillator Frequency (reset = 18432dec) bit[19:0] oscillator frequency in kHz All OfreqControl In order to achieve a correct internal operating frequency of the DSP, the nominal crystal frequency has to be written into this memory cell. 1) 2) Changes at this memory address must be validated by setting bit[0] of D0:7F11). Note: The pins SIC, SII, SID are switched to output mode if bit[0] = 1 (reset value). Micronas 33 MAS 3587F Table 3-9: D0 Control Memory Cells, continued Memory Address (hex) D0:7F41) Function PRELIMINARY DATA SHEET Mode Name Output Clock Configuration (pin CLKO) (reset = 80000hex) bit[19] CLKO configuration 0 output clock signal at CLKO 1 (reset) CLKO is tristate All OutClkConfig The CLKO output pin of the MAS 3587F can be disabled via bit [19]. bit[18] bit[17] Reserved, must be set to zero Additional division by 2 if scaler is on (bit[8] cleared) 0 (reset) oversampling factor 512/768 1 oversampling factor 256/384 Reserved, must be set to zero Output clock scaler 0 (reset) set output clock according to audio sample rate (see Table 2-1) 1 output clock fixed at 24.576 or 22.5792 MHz bit[16:9] bit[8] For a list of output frequencies at pin CLKO please refer to Table 2-1. bit[7:0] D0:7F8 Reserved, must be set to zero All SpdOutBits S/PDIF Channel Status Bits Category Code Setting (reset = 8200hex) (see Section 3.3.5. on page 37) D0:7F91) Soft Mute (reset = 0hex) bit[2] Encoder: Bitreservoir mode 0 (reset) bit reservoir is used 1 bit reservoir is kept empty All SoftMute Although the encoder uses Variable Bitrate Encoding (VBR), the bit reservoir in the MPEG bitstream is used to compensate the differences between the predefined frame sizes. If the reservoir is kept to zero, it is more easy to cut and paste complete frames for audio editing purposes, but bitstreams may grow up to 25% in the worst case. bit[1] Encoder: Pause mode 0 (reset) normal encoder operation 1 encoding process is paused The encoding process may be stopped temporarily by setting the pause bit. While in pause mode, the audio monitoring still works, but no data is encoded. When the pause bit is reset again, the encoding continues seamlessly. If the pause bit is set before enabling the encoder, a record+pause mode can be realized by the controller software. bit[0] Mute audio output 0 (reset) no mute of audio output 1 audio output is muted 1) Changes at this memory address must be validated by setting bit[0] of D0:7F11). 34 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-9: D0 Control Memory Cells, continued Memory Address (hex) D0:7FC1) D0:7FD1) D0:7FE1) D0:7FF1) 1) Function Mode Name Volume Output Control: Left Left Gain (reset = 80000hex) Volume Output Control: Left Right Gain (reset = 0hex) Volume Output Control: Right Left Gain (reset = 0hex) Volume Output Control: Right Right Gain (reset = 80000hex) Decoder Decoder Decoder Decoder out_LL out_LR out_RL out_RR Changes at this memory address must be validated by setting bit[0] of D0:7F11). Table 3-10: D0 Status Memory Cells Memory Address D0:FD0 Function MPEG Frame Counter bit[19:0] number of MPEG frames after synchronization Mode All Name MPEGFrameCount The counter will be incremented with every new frame that is encoded/decoded. With an invalid MPEG bit stream at its input while decoding (e.g. an invalid header is detected), the MAS 3587F resets the MPEGFrameCount to `0'. In encoding mode, the counter is reset on audio data time-outs and after restarting the encoder. D0:FD1 MPEG Header and Status Information bit[15] bit[14:13] reserved, must be set to zero MPEG ID, bits 12, 11 of the MPEG header 00 MPEG 2.5 (decoding only) 01 reserved 10 MPEG 2 11 MPEG 1 Bits 14 and 13 of the MPEG header 00 reserved 01 Layer 3 10 Layer 2 (decoding only) 11 Layer 1 (decoding only) CRC protection 0 bitstream protected by CRC 1 bitstream not protected by CRC Reserved CRC error (decoding only) 0 no CRC error 1 CRC error Invalid frame (decoding only) 0 no invalid frame 1 invalid frame All MPEGStatus1 bit[12:11] bit[10] bit[9:2] bit[1] bit[0] This location contains bits 15...11 of the original MPEG header and other status bits. It will be set each frame directly after the header has been encoded/decoded from the bit stream. Micronas 35 MAS 3587F Table 3-10: D0 Status Memory Cells, continued Memory Address D0:FD2 Function MPEG Header Information bit[15:12] MPEG Layer 2/3 Bitrate MPEG1, L2 MPEG1, L3 MPEG2, L2/3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 bit[11:10] free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden PRELIMINARY DATA SHEET Mode All Name MPEGStatus2 Sampling frequency in Hz MPEG1 00 01 10 11 44100 48000 32000 reserved MPEG2 22050 24000 16000 reserved MPEG2.5 11025 12000 8000 reserved bit[9] bit[8] bit[7:6] Padding bit Reserved Mode 00 01 10 11 stereo joint_stereo (intensity stereo / m/s stereo) dual channel single channel bit[5:4] Mode extension (applies to joint stereo only) 00 01 10 11 intensity stereo off on off on m/s stereo off off on on bit[3] Copyright protect bit 0 not copyright protected 1 copyright protected Copy/original bit 0/1 bitstream is a copy 1 bitstream is an original bit[2] ... 36 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-10: D0 Status Memory Cells, continued Memory Address D0:FD2 (continued) Function MPEG Header Information (continued) bit[1:0] Emphasis, indicates the type of emphasis 00 none 01 50/15 s 10 reserved 11 CCITT J.17 Mode Name MPEGStatus2 This memory cell contains the 16 LSBs of the MPEG header. It will be set directly after synchronizing to the bit stream. D0:FD3 MPEG CRC Error Counter Decoder CRCErrorCount The counter will be increased by each CRC error detected in the MPEG bitstream. It will not be reset when losing the synchronization. D0:FD4 Number of Bits in Ancillary Data Number of valid ancillary bits in the current MPEG frame. D0:FD5 ... D0:FD1 Ancillary Data (see Section 3.3.7. on page 38). Decoder Decoder NumberOfAncillaryBits AncillaryData 3.3.5. Copyright Management The controller software is responsible for the interpretation of the copyright information contained in received bitstreams and the correct setting of the copyright bits in output bitstreams. Copyright information is included in both, the S/PDIF and the MPEG bitstreams. One bit indicates if the signal is copyright protected at all. The second shows whether the signal was already copied. In the S/PDIF bitstream the copyright information is carried in the channel status bit area which is part of the S/PDIF signal (see IEC 958: "Digital Audio Interface"). The copyright information (Cp-bit) is located in bit 2 (0 = protected, 1 = no copyright), and the generation information (L-bit) is in bit 15 (0 = copy, 1 = original). The status information of received signals can be read from DSP-register 56hex, the copyright bits of originating bitstreams are controlled in memory address D0:7F8. For MPEG bitstreams, this information is located in bit 3 (copyright) and bit 2 (original) of the frame header. The firmware uses the memory cells D0:FD2 for incoming signals, D0:7F0 for outgoing signals. 3.3.5.1. Encoding of Analog or PCM-Audio In case of analog input or PCM-input at the serial interface SDI, the indication in the originating bitstream has to be set according to the application. If the copyright status is not known, the signal shall be asserted as a copyright protected original. If the S/PDIF-input is used, the copyright bits have to be evaluated. Table 3-11 gives an example in case of a DAT-Recorder input signal (category code 300hex). As the S/PDIF signal is only looped through the encoder, the copyright indication of the output must be set to the same as that of the input signal. Signals from CD (category code 100hex) are usually originals and in this case the generation bit at the output must be set to one. Table 3-11: Encoding copyright propagation with a DAT-recorder source S/PDIF in ch. status (hex) 0304 8304 0300 8300 MPEG copyright bit 0 0 MPEG original bit 0 0 S/PDIF Out Ch. Status (hex) 0204 8204 0200 8200 recording forbidden 1 0 Micronas 37 MAS 3587F 3.3.5.2. Decoding If the S/PDIF output is used, the copyright indication has to be set according to the input bitstream. Table 3-12 gives an example in case of setting the category information in the S/PDIF signal to PCM-encoder/ decoder (category code 200hex). Table 3-12: Decoding copyright propagation (PCMencoder/deocder) MPEG Copyright Bit 0 0 1 1 MPEG Original Bit 0 1 0 1 S/PDIF Out Channel Status (hex) 0204 8204 0200 8200 3.3.7. Ancillary Data 3.3.6. Variable Bitrate Encoding The encoder uses Variable Bitrate Encoding (VBR) to realize optimal compression of the audio data. The setting of a fixed bitrate is replaced with setting a quality level that preserves audio quality in critical sections and enhances compression otherwise. The minimum bitrate (in case of digital zero samples) is 32 kbit/s for MPEG 1 and 8 kbit/s for MPEG 2. The maximum bitrate is 192 kbit/s for MPEG 1 and 160 kbit/s for MPEG 2. This theoretically holds for all quality settings, but experience shows that the maximum rate does not vary too much from the average bitrate. Table 3-13 gives an overview on the average encoding bitrate that can be expected for common audio signals at different quality settings and sample rates. PRELIMINARY DATA SHEET Table 3-13: Quality setting vs. average bitrate Quality Setting "q" in D0:7F0 0 1 2 3 4 5 6 7 Average bitrate in kbit/s for fs/kHz 44.1 stereo 75 80 90 100 120 140 160 170 22.05 stereo 39 41 45 50 60 80 110 130 44.1 mono 65 68 73 80 90 105 125 140 22.05 mono 35 38 40 45 50 60 75 90 The memory fields D0:FD5...D0:FF1 contain the ancillary data. It is organized in 28 words of 16 bit each. The last ancillary bit of a frame is placed at bit 0 in D0:FD5. The position of the first ancillary data bit received can be located via the content of NumberOfAncillaryBits because int[(NumberOfAncillaryBits-1)/16] + 1 of memory words are used. Example: First get the content of 'NumberOfAncillaryBits' The first bit received from the MPEG source is at position 2 of D0:fd6; the last bit received is at the LSB of D0:FD5. 38 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-14: Content of D0:fd5 after reception of 19 ancillary bits. D0:fd5 Ancillary Data MSB 4th bit 14 5th bit 13 6th bit 12 ... 11 ... 10 ... 9 ... 8 ... 7 ... 6 ... 5 ... 4 ... 3 ... 2 17th bit 1 18th bit LSB last bit Table 3-15: Content of D0:fd6 after reception of 19 ancillary bits. D0:fd6 Ancillary Data MSB x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 first bit 1 2nd bit LSB 3rd bit 3.3.7.1. Timecode Information As the encoder uses VBR encoding, it is quite difficult to calculate the actual elapsed time in the MPEG bitstream. Therefore the encoder provides an option to insert timecodes into the MPEG bitstream. The timecode is the number of frames processed from the start of encoding. It occupies 3 bytes at the end of the ancillary data region in each MPEG frame and contains of the tag nibble 5hex followed by a 20 bit number (5hex,d4,d3,d2,d1,d0). A frame number can be translated to the absolute time in seconds by the following formulas: MPEG 1: time[s] = frame*1152/sampling freq [Hz] MPEG 2: time[s] = frame*576/sampling freq [Hz] While decoding, the controller can check the presence/ validity of the timecode information by first reading the NumberOfAncillaryBits. If the number is greater than or equal to 24 bits, two words of the ancillary data bits have to be read. D0:FD5 contains the 16 LSBs of the timecode (d3,d2,d1,d0) and D0:FD6 contains the tag nibble and the 4 MSBs (x,x,5hex,d4). If the tag nibble does not match, the timecode is not valid. As the ancillary data may contain any kind of information, it is advisable to check several successive timecodes for validity and the sequence of numbers before accepting it. 3.3.8. DSP Volume Control The digital baseband volume matrix is used for controlling the digital gain of the decoder as shown in Fig. 3- 3. This volume control is effective on both, the digital audio output and the data stream to the D/A converters. The values are in 20-bit 2's complement notation. Table 3-16 shows the proposed settings for the 4 volume matrix coefficients for stereo, left and right mono. The gain factors are given in fixed point notation as described in Section 3.3.2. The DSP volume control is available in Decoder Mode only. left audio -1 LL + -1 LR -1 RL right audio -1 RR + Fig. 3-3: Digital volume matrix Micronas to digital output and D/A 39 from MPEG decoder MAS 3587F Table 3-16: Settings for the digital volume matrix. -1.0x219 = 80000hex Memory Name Stereo (default) Mono left Mono right D0:7FC LL D0:7FD LR 0 D0:7FE RL 0 0 D0:7FF RR PRELIMINARY DATA SHEET 3.4.2. Read Codec Register 1) send command S DW W A codec_write A r3,r2 A r1,r0 A P 2) get register value S DW W A codec_read A S DR A W d1,d0 A N P -1.0 -1.0 0 -1.0 0 d3,d2 -1.0 0 -1.0 -1.0 Reading the codec registers also needs a set-up for the register address and an additional start condition during the actual read cycle. A list of status registers is given in Table 3-18. If channels are mixed, care must be taken to prevent clipping at high amplitudes. Therefore the sum of the absolute values of coefficients for one output channel must be less than or equal to 1.0. For normal operating conditions it is recommended to use the main volume control of the audio codec instead (register 00 10hex of the audio codec). 3.4. Audio Codec Access Protocol The MAS 3587F has 16-bit wide registers for the control of the audio codec. These registers are accessed via the I2C subaddresses codec_write (6Chex) and codec_read (6Dhex). 3.4.1. Write Codec Register S DW W A codec_write A r3,r2 d3,d2 A A r1,r0 d1,d0 A A P The controller writes the 16-bit value (d = d3,d2,d1,d0) into the MAS 3587F codec register (r = r3,r2,r1,r0). A list of registers is given in Table 3-17. Example: Writing the value 1234hex into the codec register with the number 00 1Bhex: 40 Micronas PRELIMINARY DATA SHEET MAS 3587F 3.4.3. Codec Registers Table 3-17: Codec control registers on I2C subaddress 6Chex Register Address (hex) Function Name CONVERTER CONFIGURATION 00 00 Audio Codec Configuration 0 dB is related to the D/A full-scale output voltage (Please refer to Section 4.6.4. on page 72) bit[15:12] bit[11:8] A/D converter left amplifier gain = n*1.5-3 [dB] A/D converter right amplifier gain = n*1.5-3 [dB] 1111 +19.5 dB 1110 +18.0 dB ... ... 0011 +1.5 dB 0010 0.0 dB -1.5 dB 0001 - 3.0 dB 0000 Microphone amplifier gain = n*1.5+21 [dB] 1111 +43.5 dB 1110 +42.0 dB ... ... 0001 +22.5 dB 0000 +21.0 dB Input selection for left A/D converter channel 0 line-in 1 microphone Enable left A/D converter Enable right A/D converter Enable D/A converter1) CONV_CONF bit[7:4] bit[3] bit[2] bit[1] bit[0] 1) The generation of the internal DC reference voltage for the D/A converter is also controlled with this bit. In order to avoid click noise, the reference voltage at pin AGNDC should have reached a near ground potential before repowering the D/A converter after a short down phase. Alternatively at least one of the A/D converters (bits [2] or [1]) should remain set during short power-down phases of the D/A. Then the DC reference voltage generation for the D/A converter will not be interrupted. INPUT MODE SELECT 00 08 Input Mode Setting bit[15] Mono switch 0 stereo input mode 1 left channel is copied into the right channel Reserved, must be set to 0 Deemphasis select 0 deemphasis off 1 deemphasis 50 s 2 deemphasis 75 s ADC_IN_MODE bit[14:2] bit[1:0] Micronas 41 MAS 3587F Table 3-17: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) Function PRELIMINARY DATA SHEET Name OUTPUT MODE SELECT D/A Converter Source Mixer 00 06 00 07 MIX ADC scale MIX DSP scale bit[15:8] Example: 00hex 20hex 40hex 7Fhex off 50% (-6 dB gain) 100% (0 dB gain) 200% (+6 dB gain) 00hex ... 7Fhex Linear scaling factor DAC_IN_ADC DAC_IN_DSP In the sum of both mixing inputs exceeds 100%, clipping may occur in the successive audio processing. 00 0E D/A Converter Output Mode bit[15] Mono switch 0 stereo through 1 mono matrix applied Invert right channel 0 through 1 right channel is inverted Reserved, must be set to 0 DAC_OUT_MODE bit[14] bit[13:0] In order to achieve more output power a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14] must be set. BASEBAND FEATURES 00 14 Bass bit[15:8] Bass range 60hex 58hex ... 08hex 00hex F8hex ... A8hex A0hex BASS +12 dB +11 dB +1 dB 0 dB -1 dB -11 dB -12 dB Higher resolution is possible, one LSB step results in a gain step of about 1/8 dB. With positive bass settings clipping of the output signal may occur. Therefore it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. The settings require: max (bass, treble) + loudness + volume 0 dB bit[7:0] Not used, must be set to 0 42 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-17: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) 00 15 Function Name Treble bit[15:8] Treble range 60hex +12 dB +11 dB 58hex ... 08hex +1 dB 0 dB 00hex -1 dB F8hex ... -11 dB A8hex -12 dB A0hex TREBLE Higher resolution is possible, one LSB step results in a gain step of about 1/8 dB. With positive treble settings, clipping of the output signal may occur. Therefore, it is not recommended to set treble to a value that, in conjunction with loudness and volume, would result in an overall positive gain. The settings require: max (bass, treble) + loudness + volume 0 dB bit[7:0] 00 1E Loudness bit[15:8] Loudness gain 44hex +17 dB +16 dB 40hex ... +1 dB 04hex 0 dB 00hex Loudness mode normal (constant volume at 1 kHz) 00hex Super Bass (constant volume at 2 kHz) 04hex Not used, must be set to 0 LOUDNESS bit[7:0] Higher resolution of loudness gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The settings should be: max (bass, treble) + loudness gain + volume 0 dB The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. Micronas 43 MAS 3587F Table 3-17: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) Function PRELIMINARY DATA SHEET Name Micronas Dynamic Bass (MDB) 00 22 MDB Effect Strength bit[15:8] 00hex 7Fhex MDB off (default) maximum MDB MDB_STR The MDB effect strength can be adjusted in 1dB steps. A value of 40hex will yield a medium MDB effect. 00 23 MDB Harmonics bit[15:8] 00hex 40hex 7Fhex no harmonics are added (default) 50% fundamentals + 50% harmonics 100% harmonics MDB_HAR The MDB exploits the psychoacoustic phenomenon of the `missing fundamental by creating harmonics of the frequencies below the center frequency of the bandpass filter (MDB_FC). This enables a loudspeaker to display frequencies that are below its cutoff frequency. The Variable MDB_HAR describes the ratio of the harmonics towards the original signal. 00 24 MDB Center Frequency bit[15:8] 2 3 ... 30 20 Hz 30 Hz 300 Hz MDB_FC The MDB Center Frequency defines the center frequency of the MDB bandpass filter (see Fig. 3-4 on page 46). The center frequency should approximately match the cutoff frequency of the loudspeakers. For high end loudspeakers, this frequency is around 50 Hz, for low end speakers around 90 Hz 00 21 MDB Shape bit[15:8] 5...30 corner frequency in 10-Hz steps (range: 50...300 Hz) MDB_SHAPE With a second lowpass filter the steepness of the falling slope of the MDB bandpass can be increased (see Fig. 3-4 on page 46). Choosing the corner frequency of this filter close to the center frequency of the bandpass filter (MDB_FC) results in a narrow MDB frequency range. The smaller this range, the harder the bass sounds. The recommended value is around 1.5 x MDB_FC MDB Switch bit[7:2] bit[1] 0 1 bit [0] reserved, must be set to zero MDB switch MDB off MDB on reserved, must be set to zero MDB_SWITCH 44 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 3-17: Codec control registers on I2C subaddress 6Chex, continued Register Address (hex) VOLUME 00 10 Volume Control bit[15:8] Volume table with 1 dB step size 7Fhex +12 dB (maximum volume) +11 dB 7Ehex ... 74hex +1 dB 0 dB 73hex -1 dB 72hex ... -113 dB 02hex -114 dB 01hex mute (reset) 00hex Not used, must be set to 0 VOLUME Function Name bit[7:0] This main volume control is applied to the analog outputs only. It is split between a digital and an analog function. In order to avoid noise due to large changes of the setting, the actual setting is internally low-pass filtered. With large scale input signals, positive volume settings may lead to signal clipping. 00 11 Balance bit[15:8] Balance range left -127 dB, right 0 dB 7Fhex left -126 dB, right 0 dB 7Ehex ... left -1 dB, right 0 dB 01hex left 0 dB, right 0 dB 00hex FFhex left 0 dB, right -1 dB ... left 0 dB, right -127 dB 81hex left 0 dB, right -128 dB 80hex BALANCE Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. 00 12 Automatic Volume Correction (AVC) Loudspeaker Channel bit[15:12] bit[11:8] 0hex 8hex 8hex 4hex 2hex 1hex AVC off (and reset internal variables) AVC on 8 s decay time 4 s decay time 2 s decay time 20 ms decay time (intended for quick adaptation to the average volume level after track or source change) AVC Note: To reset the internal variables, the AVC should be switched off and then on again during any track or source change. For standard applications, the recommended decay time is 4 s. Micronas 45 MAS 3587F Table 3-18: Codec status registers on I2C subaddress 6Dhex Register Address (hex) Function PRELIMINARY DATA SHEET Name INPUT QUASI-PEAK 00 0A A/D Converter Quasi-Peak Detector Readout Left bit[14:0] Positive 15-bit value, linear scale For example: 0000 0% 2000 25% (-12 dBFS) 4000 50% (-6 dBFS) 7FFF 100% (0 dBFS) 00 0B A/D Converter Quasi-Peak Detector Readout Right bit[14:0] OUTPUT QUASI-PEAK 00 0C Audio Processing Input Quasi-Peak Detector Readout Left bit[14:0] 00 0D Positive 15-bit value, linear scale DQPEAK_R DQPEAK_L Positive 15-bit value, linear scale QPEAK_R QPEAK_L Audio Processing Input Quasi-Peak Detector Readout Right bit[14:0] Positive 15-bit value, linear scale 3.4.4. Basic MDB Configuration With the parameters described in Table 3-17, the Micronas Dynamic Bass system (MDB) can be customized to create different bass effects as well as to fit the MDB to various loudspeaker characteristics. The easiest way to find a good set of parameter is by selecting one of the settings below, listening to music with strong bass content and adjusting the MDB parameters: - MDB_STR: Increase/decrease the strength of the MDB effect - MDB_HAR: Increase/decrease the content of low frequency harmonics - MDB_FC: Shift the MDB effect to lower/higher frequencies - MDB_SHAPE: Widen/narrow MDB frequency range (which results in a softer/harder bass sound), turn on/off the MDB Amplitude (db) Frequency MDB_FC MDB_SHAPE Fig. 3-4: Micronas Dynamic Bass (MDB): Bass boost in relation to input signal leve Table 3-19: Suggested MDB settings (all addresses and values are in hexadecimal notation) Function (Address) MDB off Low end headphones, medium effect MDB_STR (00 22) xxxx 5000 MDB_HAR (00 23) xxxx 3000 MDB_FC (00 24) xxxx 0600 MDB_SHAPE (00 21) 0000 0902 46 Micronas Signal Level PRELIMINARY DATA SHEET MAS 3587F 4. Specifications 4.1. Outline Dimensions 15 x 0.5 = 7.5 0.1 0.145 0.055 48 49 12 0.2 33 15 x 0.5 = 7.5 0.1 15 x 0.5 = 7.5 0.1 0.5 10 0.1 32 10 0.1 0.5 10 0.1 15 x 0.5 = 7.5 0.1 0.17 0.06 48 49 13.2 0.2 33 32 10 0.1 0.5 0.5 1.75 64 1 1.75 12 0.2 16 17 1.4 0.05 1.5 0.1 0.1 0.22 0.05 SPGS707000-1/1E Fig. 4-1: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions in mm (not usable for new design) 64 1 13.2 0.2 16 17 2.0 0.1 2.15 0.2 0.1 0.22 0.07 SPGS706000-6(P64)/1E Fig. 4-2: 64-Pin Plastic Metric Quad Flat Pack (PMQFP64) Weight approximately 0.4 g Dimensions in mm Micronas 47 MAS 3587F 4.2. Pin Connections and Short Descriptions not connected, leave vacant If not used, leave vacant obligatory, pin must be connected as described in application information (see Fig. 4-34 on page 81) VDD connect to positive supply VSS connect to ground Pin No. PLQFP/ PMQFP 64-pin PRELIMINARY DATA SHEET NC LV X Pin Name Type Default Connection (if not used) X Short Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AGNDC MICIN MICBI INL INR TE XTI XTO POR VSS XVSS VDD XVDD I2CVDD DVS VSENS1 DCSO1 DCSG1 DCSG2 DCSO2 VSENS2 DCEN CLKO I2CC IN IN IN IN IN IN OUT IN SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY IN IN/OUT SUPPLY SUPPLY SUPPLY SUPPLY IN/OUT IN OUT IN/OUT Analog reference voltage Input for internal microphone amplifier Bias for internal microphone Left A/D input Right A/D input Test enable Crystal oscillator (ext. clock) input Crystal oscillator output Power on reset, active low DSP supply ground Digital output supply ground DSP supply Digital output supply I2C supply I2C device address selector Sense input and power output of DC/DC converter 1 DC/DC 1 switch output DC/DC 1 switch ground DC/DC 2 switch ground DC/DC 2 switch output Sense input and power output of DC/DC converter 2 DC/DC enable (both converters) Clock output I2C clock LV LV LV LV X X LV X X X X X X X VDD LV VSS VSS LV VDD VSS LV X 48 Micronas PRELIMINARY DATA SHEET MAS 3587F Pin No. PLQFP/ PMQFP 64-pin Pin Name Type Default Connection (if not used) X LV LV LV LV LV LV VDD VSS LV LV LV LV LV LV LV LV LV LV LV X X X LV VSS VSS VSS LV LV Short Description 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I2CD SYNC VBAT PUP EOD PRTR PRTW PR PCS PI19 PI18 PI17 PI16 PI15 PI14 PI13 PI12 SOD SOI SOC SID SII SIC SPDO SIBD SIBC SIBI SPDI2 SPDI1 IN/OUT OUT IN OUT OUT OUT OUT IN IN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT OUT IN IN IN IN IN I2C data Sync output Battery voltage monitor input DC Converters Power-Up Signal PIO end of DMA, active low PIO ready to read, active low PIO ready to write, active low PIO DMA request, active high PIO chip select, active low PIO data bit[7] (MSB) PIO data bit[6] PIO data bit[5] PIO data bit[4] PIO data bit[3] PIO data bit[2] PIO data bit[1] PIO data bit[0] (LSB) Serial output data Serial output word identification Serial output clock Serial input data, interface A Serial input word identification, interface A Serial input clock, interface A S/PDIF output interface Serial input data, interface B Serial input clock, interface B Serial input word identification, interface B Active differential S/PDIF input 2 Active differential S/PDIF input 1 Micronas 49 MAS 3587F PRELIMINARY DATA SHEET Pin No. PLQFP/ PMQFP 64-pin Pin Name Type Default Connection (if not used) LV X X LV LV X X X X Short Description 54 55 56 57 58 59 60 61 62 63 64 SPDIR FILTL AVDD0 OUTL OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 IN IN SUPPLY OUT OUT SUPPLY IN SUPPLY Reference differential S/PDIF inputs 1 and 2 Feedback input for left amplifier Analog supply for output amplifiers Left analog output Right analog output Analog ground for output amplifiers Feedback for right output amplifier Analog ground Analog reference ground Internal power supply Analog supply SUPPLY SUPPLY X X 50 Micronas PRELIMINARY DATA SHEET MAS 3587F VSENS1/VSENS2 IN Sense input and power output of DC/DC converters. If the respective DC/DC converter is not used, this pin should be connected to a supply to enable proper function of the PUP-signals. DCEN IN Enable signal for both DC/DC converters. If none of the DC/DC converters is used, this pin must be connected to VSS. PUP OUT Power-up. This signal is set when the required voltages are available at both DC/DC converter output pins VSENS1 and VSENS2. The signal is cleared when both voltages have dropped below the level is set in the DCCF Register. VBAT Analog input for battery voltage supervision. IN 4.3. Pin Descriptions 4.3.1. Power Supply Pins The use of all power supply pins is mandatory to achieve correct function of the MAS 3587F. VDD, VSS Digital supply pins. XVDD, XVSS Supply for digital output pins. SUPPLY SUPPLY I2CVDD SUPPLY Supply for I2C interface circuitry. This net uses VSS or XVSS as the ground return line. PVDD SUPPLY Auxiliary pin for analog circuitry. This pin has to be connected via a 3-nF capacitor to AVDD1. Extra care should be taken to achieve a low inductance PCB line. AVDD0/AVSS0 SUPPLY Supply for analog output amplifier (output stage). AVDD1/AVSS1 SUPPLY Supply for internal analog circuits (A/D, D/A converters, clock, PLL, S/PDIF input). AVDD0/AVSS0 and AVDD1/AVSS1 should receive the same supply voltages. 4.3.4. Oscillator Pins and Clocking XTI IN XTO OUT The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Each pin should be directly connected to the crystal and to a ground-connected capacitor (see application diagram). CLKO The CLKO can drive an output clock line. OUT 4.3.2. Analog Reference Pins AGNDC Internal analog reference voltage. This pin serves as the internal ground connection for the analog circuitry. VREF Analog reference ground. All analog inputs and outputs should drive their return currents using separate traces to a ground starpoint close to this pin. Connect to AVSS1. This reference pin should be as noise free as possible. 4.3.5. Control Lines I2CC SCL I2CD SDA Standard I2C control lines. IN/OUT IN/OUT DVS IN I2C device address selector. Connect this pin either to VDD (I2C device address: 3E/3Fhex) or VSS (I2C device address: 3C/3Dhex) to select a proper I2C device address (see also Table 3-1 on page 18). 4.3.3. DC/DC Converters and Battery Voltage Supervision DCSG1/DCSG2 SUPPLY DC/DC converters switch ground. Connect using separate wide trace to negative pole of battery cell. Connect also to AVSS0/1 and VSS/XVSS, VREF. DCSO1/DCSO2 SUPPLY DC/DC converter switch connection. If the respective DC/DC converter is not used, this pin must be left vacant. 4.3.6. Parallel Interface Lines PI12..PI19 IN/OUT The PIO input pins PI12..PI19 are used as 8-bit I/O interface to a microcontroller in order to transfer compressed and uncompressed data. PI12 is the LSB, PI19 the MSB. Micronas 51 MAS 3587F 4.3.6.1. PIO Handshake Lines IN PCS The PIO chip select PCS must be set to `0' to activate the PIO in operation mode. PR IN Pin PR must be set to `1' when ready to send/receive data to/from MAS 3587F PIO pins. OUT PRTR Ready to read. This signal indicates that the MAS 3587F is able to receive data in PIO input mode. OUT PRTW Ready to write. This pin indicates that MAS 3587F has data available in PIO output mode. OUT EOD EOD indicates the end of an DMA cycle in the IC's PIO input/output mode. In 'serial' input mode it is used as Demand signal, that indicates that new input data are required. PRELIMINARY DATA SHEET 4.3.10. S/PDIF Input Interface SPDI1 IN SPDI2 IN SPDIR IN SPDI1 and SPDI2 are alternative input pins for S/ PDIF sources according to the IEC 958 consumer specification. A switch at D0:7F2 selects one of these pins at a time. The SPDIR pin is a common reference for both input lines (see Fig. 4-34 on page 81). 4.3.11. S/PDIF Output Interface SPDO OUT The SPDO pin provides an digital output with standard CMOS level that is compliant to the IEC 958 consumer specification. 4.3.12. Analog Input Interfaces In the standard MPEG-decoding DSP firmware the analog inputs are not used. However, they can be selected as a source for the D/A converters (set MIX ADC scale of the D/A Converter Source Mixer, Register 00 06hex in Table 3-15 on page 39). MICIN IN MICBI IN The MICIN input may be directly used as electret microphone input, which should be connected as described in application information (see Fig. 4-34 on page 81). The MICBI signal provides the supply voltage for these microphones. INL IN INR IN INL and INR are analog line-in input lines. They are connected to the embedded stereo A/D converter of the MAS 3587F. The sources should be AC coupled. The reference ground for these analog input pins is the VREF pin. 4.3.7. Serial Input Interface (SDI) SID DATA IN/OUT SII WORD STROBE IN/OUT SIC CLOCK IN/OUT I2S compatible serial interface A for digital audio data. In the standard firmware this interface is not used. Note: Please refer to Interface Status Register (D0:7f2) bit[0] (Table 3-9). 4.3.8. Serial Input Interface B (SDIB) SIBD DATA IN SIBI WORD STROBE IN SIBC CLOCK IN The serial interface B is used as bitstream input interface. The SIBI line must be connected to VSS in the serial decoder application. 4.3.13. Analog Output Interfaces 4.3.9. Serial Output Interface (SDO) SOD DATA OUT SOI WORD STROBE OUT SOC CLOCK IN/OUT Data, Frame Indication, and Clock line of the serial output interface. The SDO is reconfigurable and can be adapted to several I2S compliant modes. OUTL OUT OUTR OUT OUTL and OUTR are left and right analog outputs, that may be directly connected to a pair of 16 loudspeakers, to one 32 loudspeaker in a bridge mode (see Section 2.7.4. on page 10), or via 22 series resistance to the headphones as described in the application information (see Fig. 4-34 on page 81). FILTL IN FILTR IN Connection to input terminal of output amplifier. Can be used to connect capacitors from OUTL to FILTL and from OUTR to FILTR and thus implement low pass fil- 52 Micronas PRELIMINARY DATA SHEET MAS 3587F IN POR The Power-On Reset pin completely resets the MAS 3587F. The POR is an active-low signal (see Fig. 4-34 on page 81). TE IN The TE pin is for production test only and must be connected with VSS in all applications. ters to reduce the out-of-band noise of the D/A converters. 4.3.14. Miscellaneous SYNC OUT The SYNC signal indicates the detection of a frame start in the input data of MAS 3587F. Usually this signal generates an interrupt in the controller. 4.4. Pin Configurations PI12 SOD SOI SOC SID SII SIC SPDO PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SIBD SIBC SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 AGNDC MICIN MICBI INL INR TE XTI XTO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSENS1 DVS I2CVDD XVDD VDD XVSS VSS POR 32 31 30 29 28 27 26 PR PRTW PRTR EOD PUP VBAT SYNC I2CD I2CC CLKO DCEN VSENS2 DCSO2 DCSG2 DCSG1 DCSO1 MAS 3587F 25 24 23 22 21 20 19 18 17 Fig. 4-3: PLQFP64/PMQFP64 package (Top view) Micronas 53 MAS 3587F 4.5. Internal Pin Circuits I2CVDD PRELIMINARY DATA SHEET TTLIN N Fig. 4-4: Input pins PCS, PR VSS Fig. 4-10: Input/output pins I2CC, I2CD VSENS Fig. 4-5: Input pin TE, DVS, POR P DCSO N DCSG Fig. 4-11: Input/output pins DCSO1/2, DCSG1/2, VSENS1/2 Fig. 4-6: Input pin DCEN XVDD XVDD P N N XVSS Fig. 4-7: Input/output pins SOC, SOI, SOD, PI12...PI19, SPDO P XVSS Fig. 4-12: Output pins PRTW, EOD, PRTR, CLKO, SYNC, PUP AVDD XVDD P XTI P N N Enable N AVSS Fig. 4-13: Clock oscillator XTI, XTO P P XTO N XVSS Fig. 4-8: Input pins SI(B)C, SI(B)I, SI(B)D Fig. 4-9: Input pins SIBC, SIBI, SIBD 54 Micronas PRELIMINARY DATA SHEET MAS 3587F MICIN INL INR XVDD - + A D SPDI1, SPDI2 SPDIR - + XVDD Bias AGNDC Fig. 4-14: Analog input pins MICIN, INL, INR Fig. 4-18: S/PDIF inputs AGNDC + - MICBI VBAT VREF Fig. 4-15: Microphone bias pin (MICBI) + - VSS = VSS programmable FILTL(R) Fig. 4-19: Battery voltage monitor VBAT D A I - + OUTL(R) AGNDC Fig. 4-16: Analog outputs OUTL(R) and connections for filter capacitors FILTL(R) + - AGNDC 1.25 V VREF Fig. 4-17: Analog ground generation with pin to connect external capacitor Micronas 55 MAS 3587F 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA Parameter Ambient operating temperature - operating conditions - extended temperature range1) TC_LQFP TC_MQFP TS PTOT Case temperature PLQFP64 Case temperature PMQFP64 Storage Temperature Power dissipation VDD, XVDD, AVDD0/1, I2CVDD VDD, XVDD, I2CVDD AVDD0/12) I2CC, I2CD 0 -40 Pin Name Min. PRELIMINARY DATA SHEET Max. Unit 70 70 80 TBD 125 650 C C C C C mW -40 -40 -40 VSUP Supply voltage -0.3 6 V VII2C VIdig IIdig VIana IIana IOaudio IOdig IOdcdc1 IOdcdc2 1) 2) 3) 4) Input voltage, I2C-Pins Input voltage, all digital inputs Input current, all digital inputs Input voltage, all analog inputs Input current, all analog inputs Output current, audio output3) Output current, all digital outputs4) Output current DCDC converter 1 Output current DCDC converter 2 -0.3 -0.3 -20 -0.3 -5 6 VSUP +0.3 +20 VSUP + 0.3 +5 0.2 +50 1.5 1.5 V V mA V mA A mA A A OUTL/R -0.2 -50 DCSO1 DCSO2 The functionality of the device in the "extended temperature range" was checked by electrical characterization on sample base. Data sheet parameters are valid for "operating conditions" only. Both AVDD0 and AVDD1 have to be connected together! These pins are not short-circuit proof! Total chip power dissipation must not exceed absolute maximum rating Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 56 Micronas PRELIMINARY DATA SHEET MAS 3587F 4.6.2. Recommended Operating Conditions Table 4-1: Temperature range and supply voltages Symbol TA Parameter Ambient operating temperature - operating conditions - extended temperature range1) VSUPD1 VSUPD2 Digital supply voltage (MPEG decoder) Digital supply voltage (MPEG 1 encoder) 48, 32 kHz 44.1 kHz Digital supply voltage (MPEG 2 encoder) VSUPI2C VSUPA I2C bus supply voltage Analog audio supply voltage Analog audio supply voltage in relation to the digital supply voltage VSUPx PIN supply voltage PIN supply voltage in relation to digital supply voltage 1) Pin Name Min. Typ. Max. Unit 0 -40 VDD, XVDD 2.5 2.7 70 70 3.9 C C V 3.5 3.3 2.7 I2CVDD AVDD0/1 VSUPDn2) at VDD 2.2 0.62 3.7 3.5 2.9 3.9 3.9 3.9 3.9 V V VSUPDn 2.7 3.9 1.6 XVDD 2.5 0.62 3.9 1.6 V VSUPDn The functionality of the device in the "extended temperature range" was checked by electrical characterization on sample base. Data sheet parameters are valid for "operating conditions" only. 2) n = 1,2 Micronas 57 MAS 3587F Table 4-2: Reference frequency generation and crystal recommendation Symbol Parameter Pin Name Min. PRELIMINARY DATA SHEET Typ. Max. Unit External Clock Input Recommendations fCLK VCLKI Clock frequency Clock amplitude of external clock fed into XTI at VSUPA = 2.2 V Clock amplitude of external clock fed into XTI at VSUPA = 2.7 V Clock amplitude of external clock fed into XTI at VSUPA = 3.3 V Clock amplitude of external clock fed into XTO at VSUPA = 2.2 V Clock amplitude of external clock fed into XTO at VSUPA = 2.7 V Clock amplitude of external clock fed into XTO at VSUPA = 3.3 V Duty cycle Crystal Recommendations TA fP Ambient operating temperature Load resonance frequency at CI = 20 pF Accuracy of frequency adjustment Frequency variation vs. temperature Equivalent series resistance Shunt (parallel) capacitance XTI, XTO XTI, XTO XTO XTI, XTO XTI 13.02) 0.7 18.432 20.01) 1.05 MHz VPP 0.55 1.5 0.45 1.75 1.25 2.2 0.75 2.7 0.55 3.3 45 50 55 % -40 18.432 70 C MHz f/fS f/fS REQ C0 1) 2) -50 -50 12 3 50 50 30 5 ppm ppm pF extended to 28 MHz by divider 1/1.5 (refer to Table 3-3 on page 20) depending on mode (refer to Table 4-3) 58 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 4-3: Input clock frequency Symbol fCLK Parameter MPEG 1 Encoder MPEG Decoder MPEG 2 Encoder Pin Name XTI Min. 11.0 13.7 Typ. Max. Unit MHz MHz Table 4-4: Input levels Symbol IIL IIH IIL IIH IILD IIHD Parameter Input low voltage at VSUPI2C = 2.5...3.9 V Input high voltage at VSUPI2C = 2.5...3.9 V Input low voltage at VSUPI2C = 2.5...3.9 V Input high voltage at VSUPI2C = 2.5...3.9 V Input low voltage Input high voltage PI, SI(B)I, SI(B)C, SI(B)D, PR, PCS, TE, DVS POR, DCEN 0.9 0.3 VSUPD -0.5 Pin Name I2CC, I2CD 1.4 0.2 Min. Typ. Max. 0.3 Unit V V V V V V Micronas 59 MAS 3587F Table 4-5: Analog input and output recommendations Symbol Parameter Pin Name Min. PRELIMINARY DATA SHEET Typ. Max. Unit Analog Reference CAGNDC1 CAGNDC2 CPVDD Analog filter capacitor Ceramic capacitor in parallel Capacitor for analog circuitry PVDD 3 AGNDC 1.0 3.3 10 F nF nF Analog Audio Inputs CinAD CinMI CLMICBI DC-decoupling capacitor at A/Dconverter inputs DC-decoupling capacitor at microphone-input Minimum-Capacitance at microphone bias INL/R MICIN MICBI 3.3 390 390 nF nF nF Analog Audio Filter Outputs CFILT Filter capacitor for headphone amplifier high-Q type, NP0 or C0G material FILTL/R OUTL/R -20% 470 +20% pF Analog Audio Output ZAOL_HP Analog output load with stereo headphones OUTL/R 16 100 DC/DC-Converter External Circuitry (please refer to application example) C1 VTH L VSENS blocking (<100 m ESR) Schottky diode threshold voltage Ferrite core coil inductance VSENS1/2 DCSO1/2 VSENS1/2 DCSO1/2 330 0.39 22 F V H pF S/PDIF Interface Analog Input CSPI S/PDIF coupling capacitor SPDI1/2 SPDIR 100 nF 60 Micronas PRELIMINARY DATA SHEET MAS 3587F 4.6.3. Digital Characteristics at T = TA, VSUPDn, VSUPA, VSUPx = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C, in PMQFP64/ PLQFP64 package Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Digital Supply Voltage ISUPD1 Current consumption (MPEG decoding) VDD, XVDD, I2CVDD 35 18 10 ISUPD2 Current consumption (MPEG encoding) 130 63 ISTANDBY Total current at stand-by 10 A mA 2.5 V, sampling frequency 32 kHz 2.5 V, sampling frequency 24 kHz 2.5 V, sampling frequency 12 kHz 3.5 V, sampling frequency 32 kHz 2.7 V, sampling frequency 24 kHz DSP off, Codec off, DC /DC off, A/D and D/A off, no I2C access Digital Outputs and Inputs ODigL ODigH Output low voltage Output low voltage PI, SOI, SOC, SOD, EOD, PRTR, PRTW, CLKO, SYNC, PUP, SPDO all digital Inputs -1 0.3 VSUPD -0.3 V V Iload = 2 mA Iload = -2 mA ZDigI IDLeak Input impedance Digital input leakage current 7 1 pF A 0 V < Vpin < VSUPD Micronas 61 MAS 3587F 4.6.3.1. I2C Characteristics at T = 25C, VSUPI2C = 2.5...3.6 V, in PMQFP64/PLQFP64 package Symbol Parameter Pin Name Min. Typ. Max. PRELIMINARY DATA SHEET Unit Test Conditions I2C Input Specifications fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 VI2CIL VI2CIH tW Upper limit I2C bus frequency operation I2C START condition setup time I2C STOP condition setup time I2C clock low pulse time I C clock high pulse time I2C data setup time before rising edge of clock I2C data hold time after falling edge of clock I2C output low voltage I2C output high leakage current I2C data output hold time after falling edge of clock I2C data output setup time before rising edge of clock I2C input low voltage I2C input high voltage Wait time 2 I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC; I2CD I2CC, I2CD I2CC, I2CD 400 300 300 1250 1250 80 80 0.4 1 20 250 0.3 0.6 0 0.5 4 kHz ns ns ns ns ns ns V A ns ns VSUPI2C VSUPI2C ms fI2C = 400 kHz Iload = 3 mA 1/fI2C tI2C4 H L tI2C3 I2CC tI2C1 tI2C5 tI2C6 tI2C2 H L I2CD as input tI2COL2 tIC2OL1 H L I2CD as output Fig. 4-20: I2C timing diagram 62 Micronas PRELIMINARY DATA SHEET MAS 3587F 4.6.3.2. Serial (I2S) Input Interface Characteristics (SDI, SDIB) at T = TA, VSUPDn, VSUPA, VSUPx = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C, in PMQFP64/ PLQFP64 package Symbol tSICLK Parameter I2S clock input clock period Pin Name SI(B)C Min. Typ. 325 Max. Unit ns Test Conditions fS = 48 kHz Stereo, 32 bits per sample (for demand mode see Table 4-6 on page 64) tSIDS I2S data setup time before rising edge of clock (for continuous data stream: falling edge) I2S data hold time I2S ident setup time before rising edge of clock (for continuous data stream: falling edge) I2S ident hold time Burst wait time SI(B)C, SI(B)D 50 ns tSIDH tSIIS SI(B)D SI(B)C, SI(B)I 50 50 ns ns tSIIH tbw SI(B)I SI(B)C, SI(B)D 50 480 ns tSICLK SI(B)C H L SI(B)I H L tSIIS SI(B)D H L tSIIH tSIDS Fig. 4-21: Serial input of I2S signal tSIDH Micronas 63 MAS 3587F PRELIMINARY DATA SHEET tSTART H L tSTOP EOD tSICLK H SI(B)C L H SI(B)I L SI(B)D H L tSIDS tSIDH Fig. 4-22: Continuous data stream at serial input A or B. In this mode, the word strobe SI(B)I is not used and the data are read at the falling edge of the clock (bit 2 in D0:7F1 is set). Table 4-6: Maximum allowed sample clock frequency in Demand Mode fSample (kHz) 48, 32 44.1 24, 16 fCmax (MHz) 6.144 5.6448 3.072 min. tSICLK (ns) 162 Table 4-6: Maximum allowed sample clock frequency in Demand Mode fSample (kHz) 22.05 12, 8 fCmax (MHz) 2.8224 1.536 1.4112 min. tSICLK (ns) 354 651 708 177 11.025 325 64 Micronas PRELIMINARY DATA SHEET MAS 3587F 7DEOH Allowed transmission delays of external data source Symbol Parameter Pin Name EOD Min. Typ. Max. 3.1 5.7 4.2 9.2 23.1 25.6 34.8 38.4 Allowed delay time before stop of serial data transmission after deassertion of signal at EOD Unit ms ms ms ms ms ms ms ms ms Test Conditions 48 kHz/s, 320 kbit/s 48 kHz/s, 64 kbit/s 24 kHz/s, 320 kbit/s 24 kHz/s, 32 kbit/s 12 kHz/s, 64 kbit/s 12 kHz/s, 16 kbit/s 8 kHz/s, 64 kbit/s 8 kHz/s, 8 kbit/s Clock rate of input data 1 Mbit/s tSTART48-320 Allowed delay time before start of serial data tSTART48-64 transmission after assertion of signal at EOD tSTART24-320 tSTART24-32 tSTART12-64 tSTART12-16 tSTART8-64 tSTART8-8 tSTOP EOD 1.3 4.6.3.3. Serial Output Interface Characteristics (SDO) at T = TA, VSUPDn, VSUPA, VSUPx = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C, in PMQFP64/ PLQFP64 package Symbol tSOCLK tSOISS tSOODC Parameter I2S clock output frequency I2S word strobe delay time after falling edge of clock I2S data delay time after falling edge of clock Pin Name SOC SOC, SOI SOC, SOD 0 0 Min. Typ. 325 Max. Unit ns ns ns Test Conditions fS = 48 kHz Stereo 32 bits per sample tSOCLK H SOC L SOI H L tSOISS SOD H L tSOISS tSOODC Fig. 4-23: Serial output interface timing. Micronas 65 MAS 3587F PRELIMINARY DATA SHEET Vh SOC Vl Vh SOD Vl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 76543210 SOI Vh Vl left 16-bit audio sample right 16-bit audio sample Fig. 4-24: Sample timing of the SDO interface in 16 bit/sample mode. D0:7F1 settings are: Bit 14 = 0 (SOC not inverted), bit 11 = 1 (SOI delay), bit 5 = 0 (word strobe not inverted), bit 4 = 1 (16 bits/sample). SOC Vh Vl ... ... Vh SOD Vl Vh 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 SOI Vl left 32-bit audio sample right 32-bit audio sample Fig. 4-25: Sample timing of the SDO interface in 32 bit/sample mode. D0:7F1 settings are: Bit 14 = 0 (SOC not inverted), bit 11 = 0 (no SOI delay), bit 5 = 1 (word strobe inverted), bit 4 = 0 (32 bits/sample). 66 Micronas PRELIMINARY DATA SHEET MAS 3587F 4.6.3.4. S/PDIF Input Characteristics at T = TA, VSUPDn, VSUPA,VSUPx = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C, in PMQFP64/ PLQFP64 package. Symbol VS fs1 fs2 fs3 tP tR tF Parameter Signal amplitude Bi-phase frequency Bi-phase frequency Bi-phase frequency Bi-phase period Rise time Fall time Duty cycle tH1,L1 Pin Name SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI1, SPDI2, SPDIR SPDI SPDI 0 0 40 81 50 Min. 200 Typ. 500 2.048 2.822 3.072 326 65 65 60 163 Max. 1000 Unit mVpp MHz MHz MHz ns ns ns % ns 1000 ppm, fs = 48 kHz 1000 ppm, fs = 44.1 kHz 1000 ppm, fs = 32 kHz at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at bit value = 1 and fs = 48 kHz minimum/maximum pulse duration with a level above 90% or below 10% and at fs = 48 kHz minimum/maximum pulse duration with a level above 90% or below 10% and at fs = 48 kHz Test Conditions tH0,L0 SPDI 163 244 ns tR tH1 Bit value = 1 tH0 Bit value = 0 tP tF tL1 tL0 Fig. 4-26: Timing of the S/PDIF input Micronas 67 MAS 3587F 4.6.3.5. S/PDIF Output Characteristics PRELIMINARY DATA SHEET at T = TA, VSUPDn, VSUPA, VSUPx = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 C, in PMQFP64/ PLQFP64 package. Symbol fs1 fs2 fs3 tP tR tF Parameter Bi-phase frequency Bi-phase frequency Bi-phase frequency Bi-phase period Rise time Fall time Duty cycle tH1,L1 Pin Name SPDO SPDO SPDO SPDO SPDO SPDO SPDO SPDO 0 0 50 163 Min. Typ. 3.072 2.822 2.048 326 2 2 Max. Unit MHz MHz MHz ns ns ns % ns minimum/maximum pulse duration with a level above 90% or below 10% and at fs = 48 kHz minimum/maximum pulse duration with a level above 90% or below 10% and at fs = 48 kHz Test Conditions fs = 48 kHz fs = 44.1 kHz fs = 32 kHz at fs = 48 kHz, (highest sampling rate) Cload = 10 pF Cload = 10 pF tH0,L0 SPDO 326 ns VS Signal amplitude SPDO VSUPD tR tH1 Bit value = 1 tH0 Bit value = 0 tP tF tL1 tL0 Fig. 4-27: Timing of the S/PDIF output 68 Micronas PRELIMINARY DATA SHEET MAS 3587F 7DEOH DMA input timing Symbol tst tr tpd tset th trtrq tpr trpr teod teodq Pin Name PR, EOD PR, RTR PR, PI[19:12] PI[19:12] PI[19:12] RTR PR PR, RTR PR, EOD EOD Min. 0.010 40 120 160 160 200 480 160 40 2.5 160 500 30000 Max. 2000 160 480 Unit 4.6.3.6. PIO as Parallel Input Interface: DMA Mode In decoding mode, the data transfer can be started after the EOD pin of the MAS 3587F is set to "high". After verifying this, the controller signalizes the sending of data by activating the PR line. The MAS 3587F responds by setting the RTR line to the "low" level and reads the data at PI[19:12]. After RTR is set to high again, the controller sets PR to low. The next data word write operation will be initialized again by setting the PR line via the controller. Please refer to Figure 4- 28 for the exact timing The procedure above will be repeated until the MAS 3587F sets the EOD signal to "0" which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again and then repeat the procedure to send the next block of data. The DMA buffer is 30 bytes long. s ns ns ns ns ns ns ns ns s tst tr tpd trtrq trpr teod teodq high EOD tpr PR low high low high RTR tset PI[19:12] Byte 1 Byte 30 MAS 3587F latches the PIO data th high low low Fig. 4-28: Handshake protocol for writing MPEG data to the PIO-DMA Micronas 69 MAS 3587F 4.6.3.7. PIO As Parallel Input Interface: Program Download Mode Handshaking for PIO input in Program Download Mode is accomplished through the RTR, PCS, and PI12..PI19 signal lines (see Fig. 4-29). The PR line should be set to low level. The MAS 3587F will drive RTR low as soon as it is ready to receive a byte and RTR will stay low until one byte has been written. Writing of a byte is performed with a PCS pulse, driven by the microcontroller. The MAS 3587F reads data after the falling edge of PCS and will finish the cycle by setting RTR to high level after the rising edge of PCS. The next data transfer initialized by the MAS 3587F by driving the RTR line. Table 4-9: PIO Program Download Mode timing Symbol t0 t1 t2 t3 t4 t5 Pin Name RTR, PCS PCS PCS, RTR RTR PI PI Min. 0 150 0 0.4 50 50 30 5 Max. Unit PRELIMINARY DATA SHEET s ns ns s ns ns t0 RTR t1 t2 t3 PIxx t5 PCS t4 Fig. 4-29: Input timing for Program Download Mode 70 Micronas PRELIMINARY DATA SHEET MAS 3587F Table 4-10: PIO output mode timing Symbol t0 t1 t2 t3 t4 t5 teod teodq Pin Name EOD, PR PR, PI PI, RTW RTW, PR PR, RTW RTW, PR Min. 0.010 110 18 18 90 35 140 2.5 8000 260 Max. 2000 310 55 Unit 4.6.3.8. PIO as Parallel Output Interface: DMA Mode In encoding mode, the MAS 3587F signals available data by setting the EOD pin to "high". After verifying this, the controller signalizes its capability to receive one byte of data by activating the PR line. The MAS 3587F responds by setting the RTW line to the "low" level when the actual byte is set on the data lines PI[19:12]. After PR is set to "low" level, the RTW line is set to "high" again. The next data word write operation will be initialized again by setting the PR line via the controller. Please refer to Figure 4-30 for the exact timing. The procedure above will be repeated until the MAS 3587F sets the EOD signal to "0" which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again and then repeat the procedure to receive the next block of data. The DMA buffer is currently 30 bytes long. In order to transfer the worst case data rate of 192 kbit/s, the controller must react sufficiently fast. The mean response times (t0, t3, t5) must be faster than 10 ms. Due to internal buffering in the MAS 3587F, this time can be expanded up to 4.8 ms once within each frame (see Table 2-2 on page 16) in any case. s ns ns ns ns ns ns s t0 t1 t2 t3 t4 t5 teod teodq high EOD low high PR low high RTW low high PI[19:12] Byte 1 Byte 30 low Fig. 4-30: Handshake protocol for reading MPEG data from the PIO-DMA Micronas 71 MAS 3587F 4.6.4. Analog Characteristics PRELIMINARY DATA SHEET at T = TA VSUPDn, VSUPx = 2.5...3.6 V, VSUPA = 2.2 ... 3.6 V, fCrystal = 13...20 MHz, typical values at TA = 25 C and fCRYSTAL = 18.432 MHz, in PMQFP64/PLQFP64 package Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Supply IAVDD IQOSC Current consumption analog audio Current consumption crystal oscillator AVDD0/1 AVDD0/1 5 200 mA A VSUPA = 2.2 V, Mute Codec = off DSP = off DC/DC = on Codec = off DSP = off DC/DC = off ISTANDBY 10 Crystal Oscillator VDCCLK VACLK CIN ROUT DC voltage at oscillator pins Clock amplitude Input capacitance Output resistance XTO XTI, XTO 0.5 3 220 125 94 Analog References VAGNDC Analog Reference Voltage AGNDC V RL >> 10 M, referred to VREF VSUPA 1.1 1.3 1.6 VMICBI Bias voltage for microphone MICBI 1.8 2.13 2.62 RMICBI IMAX Source resistance Maximum current microphone bias MICBI MICBI 300 180 A VSUPA >2.2 V Bits 15, 14 in Reg. 6Ahex 00 >2.2 V >2.4 V >3.0 V VSUPA >2.2 V >2.4 V >3.0 V Bits 15, 14 in Reg. 6Ahex 00 01 10 Bits 15, 14 in Reg. 6Ahex 00 01 10 0.5 VSUPA -0.5 VSUPA VPP pF VSUPA = 2.2 V VSUPA = 2.7 V VSUPA = 3.3 V if crystal is used 72 Micronas PRELIMINARY DATA SHEET MAS 3587F Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Audio Inputs VAI Analog line input clipping level (at minimum analog input gain,i.e. -3 dB) INL/R 2.2 2.6 3.2 VMI Microphone input clipping level (at minimum analog input gain, i.e. +21 dB) MICIN 141 167 282 RinAI Analog line input resistance INL/R 97 20 67 RinMI Microphone input resistance MICIN 94 8 94 SNRAI Signal-to-noise ratio of line input Signal-to-noise ratio of microphone input Total harmonic distortion of analog inputs INL/R 74 dB(A) k k mVpp Vpp VSUPA >2.2 V >2.4 V >3.0 V VSUPA >2.0 V >2.4 V >3.0 V Bits 15, 14 in Reg. 6Ahex 00 01 10 Bits 15,14 in Reg. 6Ahex 00 01 10 at minimum analog input gain, i.e. -3 dB at maximum analog input gain, i.e. +19.5 dB not selected at minimum analog input gain, i.e. -21 dB at maximum analog input gain, i.e. +43.5 dB not selected BW = 20 Hz...20 kHz, analog gain = 0 dB, input 1 kHz at VAI-20 dB BW = 20 Hz...20 kHz, analog gain = +21 dB, input 1 kHz at VMI-20 dB BW = 20 Hz...20 kHz, analog gain = 0 dB, resp. 24 dB, input 1 kHz at -3 dBFS = VAI-6 dB resp. VMI-6 dB f = 1 kHz, sine wave, analog gain = 0 dB, input = -3 dBFS 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms SNRMI MICIN 73 dB(A) THDAI INL/R MICIN 0.01 0.02 % XTALKAI Crosstalk attenuation left/right channel (analog inputs) Power supply rejection ratio for analog audio inputs INL/R MICIN AVDD0/1, INL/R MICIN 80 dB PSRRAI 45 20 dB dB Micronas 73 MAS 3587F PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Audio Output VAO1 Analog output voltage AC OUTL/R RL1 k Input = 0 dBFS digital VSUPA at 0 dB output gain 1.56 1.84 2.27 at +3 dB output gain 2.20 2.60 3.20 dVAO1 Deviation of DC-level at analog output for AGNDCvoltage Analog output voltage AC OUTL/R -20 20 mV Vpp Vpp >2.2 V >2.4 V >3.0 V >2.2 V >2.6 V >3.2 V Bits 15, 14 in Reg 6Ahex 00 01 10 00 01 10 VAO2 OUTL/R RLis 16 Headphone and 22 seriesresistor Input = 0 dBFS digital (see Fig. 4-34 on page 81) VSUPA Bits 15, 14 in Reg 6Ahex 00 01 10 00 01 10 at 0 dB output gain 1.56 1.84 2.27 Vpp >2.2 V >2.4 V >3.0 V at +3 dB output gain 2.00 2.40 3.00 Vpp >2.2 V >2.6 V >3.2 V RoutAO SNRAO Analog output resistance Signal-to-noise ratio of analog output OUTL/R OUTL/R 94 6 dB(A) analog gain = +3 dB, Input = 0 dBFS digital RL16 BW = 20 Hz...20 kHz, analog gain = 0 dB input = -20 dBFS for RL16 plus 22 series resistor (see Fig. 4-34 on page 81) for RL1 k A-weighted BW = 20 Hz...22 kHz , no digital input signal, analog gain = mute THDAO Total harmonic distortion (headphone) OUTL/R 0.03 0.05 % 0.003 LevMuteAO Mute level OUTL/R -113 0.01 % dBV 74 Micronas PRELIMINARY DATA SHEET MAS 3587F Symbol XTALKAO Parameter Crosstalk attenuation left/right channel (headphone) Pin Name OUTLR Min. Typ. 80 Max. Unit dB Test Conditions f = 1 kHz, sine wave, OUTL/R: RL16 (see Fig. 4-34 on page 81) analog gain = 0 dB input = -3 dBFS 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms PSRRAO Power supply rejection ratio for analog audio outputs AVDD0/1 OUTL/R 70 35 dB dB Micronas 75 MAS 3587F 4.6.5. DC/DC Converter Characteristics PRELIMINARY DATA SHEET at T = TA, Vin = 1.2 V, Voutn = 3.0 V, fclk = 18.432 MHz, fsw = 384 kHz, PWM-mode, L = 22 H, in PMQFP64/ PLQFP64 package (unless otherwise noted) Typ. values for TA = 25 C Symbol VIN VIN Parameter Minimum start-up input voltage Minimum operating input voltage DC1 DC2 DC1 DC2 VOUT Programmable output voltage range Output voltage tolerance Output current 1 battery cell Output current 2 battery cells Line regulation Load regulation Maximum efficiency Switching frequency DCSOn 297 VSENSn VSENSn 0.7 -1.8 95 384 576 VSENSn 2.0 0.7 0.8 1.1 1.2 3.5 V V V Pin Name * Min. Typ. 0.9 Max. Unit V Test Conditions ILOAD 1 mA, DCCF = 5050hex (reset) 1) ILOAD = 50 mA, DCCF = 5050hex (reset) ILOAD = 200 mA, DCCF = 5050hex (reset) Voltage settings in DCCF register (I2C subaddress 76hex) ILOAD = 20 mA TA = 25 C 2) VIN = 0.9...1.5 V, 330 F VIN = 1.8...3.0 V, 330 F ILOAD = 20 mA ILOAD = 20...200 mA VIN = 2.4 V, VOUT = 3.5 V (see Section 2.9.2. on page 12), (see Table 3-3 on page 20) VSENSn < 1.9 V 3) VOTOL ILOAD1 ILOAD2 dVOUT/ dVIN/VOUT dVOUT/ VOUT hmax fswitch VSENSn VSENSn -4 4 200 600 % mA mA %/V % % kHz fstartup IsupPFM1 IsupPFM2 IsupPWM1 IsupPWM2 Ilnmax Switching frequency during start-up Supply current in PFM mode DCSOn VSENS1 VSENS2 250 75 135 265 325 1 0.4 kHz A Supply current in PWM mode VSENS1 VSENS2 A VSENSn 3) 4) NMOS switch current limit (low side switch) PMOS switch turnoff current (rectifier switch) NMOS switch on resistance (low side switch) DCSOn, DCSGn DCSOn, VSENSn DCSO1, DCSG1 DCSO2, DCSG2 A PWM-mode PFM-mode Ilptoff RON 70 170 280 mA m 76 Micronas PRELIMINARY DATA SHEET MAS 3587F Symbol ILEAK 1) 2) 3) 4) Parameter Leakage current Pin Name DCSOn, DCSGn Min. Typ. 0.1 Max. Unit A Test Conditions Converters off, no load Since the regulators are bootstrapped, once started they will operate down to 0.7 V input voltage PFM-mode regulates aprox. 1% higher Current into VSENSn Pin. VIN > VOUT+0.4 V; no DC/DC-Converter switching action present Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.4. on page 72) Micronas 77 MAS 3587F 4.6.6. Typical Performance Characteristics PRELIMINARY DATA SHEET Efficiency vs. Load Current DCDC1 (VOUT = 3.5 V) 100 3.0 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.5 V) 3.0 V 80 Efficiency (%) 1.8 V Efficiency (%) 80 1.8 V 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 40 40 20 20 0 10-4 10-3 10-2 10-1 1 0 10-4 10-3 10-2 10-1 1 Load Current (A) Load Current (A) Efficiency vs. Load Current DCDC1 (VOUT = 3.0 V) 100 2.4 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.0 V) 2.4 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 10-3 10-2 10-1 0 10-4 10-3 10-2 10-1 1 0 10-4 1 Load Current (A) Fig. 4-31: Efficiency vs. Load Current Load Current (A) 78 Micronas PRELIMINARY DATA SHEET MAS 3587F Efficiency vs. Load Current DCDC1 (VOUT = 2.2 V) 100 1.5 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 2.2 V) 1.5 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 0 10-4 10 -3 10 -2 10 -1 1 0 10-4 10-3 10-2 10-1 1 Load Current (A) Load Current (A) Maximum Load Current vs. Input Voltage 0.8 DCDC1 Vout: 2.2 V 3.0 V 3.5 V PFM PWM 0.8 Maximum Load Current vs. Input Voltage DCDC2 Maximum Load Current (A) Vout: 2.2 V 3.0 V 3.5 V PFM 0.4 PWM Maximum Load Current (A) 0.6 0.6 0.4 0.2 0.2 0 0.0 1.0 2.0 3.0 Input Voltage (V) Fig. 4-32: Maximum Load Current vs. Input Voltage 0 0.0 1.0 2.0 3.0 Input Voltage (V) Micronas 79 MAS 3587F Note: Efficiency is measured as VSENSn x ILOAD / (Vin x Iin). IAVDD is not included (Oscillator current) PRELIMINARY DATA SHEET Loadregulation at VOUT = 2.7 V, 2.5 V 2.75 2.7 Output Voltage (V) 2.65 2.6 2.55 2.5 2.45 DCDC1 2.4 0 50 100 150 200 Load Current (mA) 2.9 0 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 3.55 3.5 Output Voltage (V) 3.45 3.4 3.05 3.0 2.95 Loadregulation at VOUT = 3.0 V, 3.5 V 1.5 V 1.5 V VIN: 1.5 V 1.2 V 0.9 V 0.9 V DCDC1 50 100 150 200 Load Current (mA) Fig. 4-33: Loadregulation No-Load Battery Current VOUT = 3.0 V 10 Both DCDC running in PWM One DCDC running in PFM Battery Current (mA) 8 6 4 2 0 0.5 1.0 1.5 2.0 2.5 3.0 Input Voltage (V) 80 Micronas Micronas 81 - MMC/SDI-Card or SMC/CF2+ used as storage media - Dashed lines show optional (external) devices 4.7. Typical Application in a Portable Player PRELIMINARY DATA SHEET Fig. 4-34: Application circuit of the MAS 3587F. For connections of the DC/DC converters, please refer to Fig. 4-35 on page 82. VDC2 VDC2 Serial memory device e.g. SDI-Card Portable radio telephone Parallel memory device e.g. SmartMediaCard 3 MPEG, CELP, SC4 8 DigiAmp MD-recorder IEC 60958 MPEG, SC4 2 D 100 k 3 D Reference clock VDC2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D SOD SPDO SIC SII SID SOC SOI PI12 PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCSQ 10k SIBD SIBC DAB-receiver DVD-player ADR-receiver 75 22 75 MPEG (IEC 61937) 100n 100n 470p 100n SIBI SPDI2 SPDI1 SPDIR FILTL AVDD0 OUTL 220u L Headphone > 16 R 1.5k 100 1.5k 6.8n 22 100 6.8n 22u 3n A 10n 470p OUTR AVSS0 FILTR AVSS1 VREF PVDD AVDD1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 I2CVDD VSENS1 MICIN AGNDC 63 64 PORQ XVDD MICBI XVSS VSS XTI XTO VDD DVS INL INR TE 32 31 30 29 28 27 26 PR PRTWQ PRTRQ EODQ PUP VBAT SYNC I2CD I2CC CLKO DCEN VSENS2 DCSO2 DCSG2 DCSG1 DCSO1 See figure caption 220p 1n 18p 18p 390 n 390n A 18.432 MHz 3.6...5.6 k 3.3 n MIC 390p separate trace Tape recorder FM radio D A 1u Place VDD / XVDD -filter capacitors above ground plane 390n 390p 10k VDC1 VDC2 D 4u7 D 1.5u 1.5u Option for I2C-address connect to VSS or I2CVDD A D 1n 4k7 VDC2 4k7 5 PIO-control 220u MAS 3587F 25 24 23 22 21 20 19 18 17 C 1 Place all ceramic capacitors as close as possible to IC pins VDC1 470p capacitorss should be high-Q (NP0 or C0G) A 3u3 10n 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Star point ground connection very close to pins DCSG1 and DCSG2 MAS 3587F MAS 3587F 4.8. Recommended DC/DC Converter Application Circuit Configuration 1 (see Fig. 2-11 on page 14) VBAT DCSO1 PRELIMINARY DATA SHEET L1 = 22 H D1, Schottky AVDD0/1 VSENS1 VDC1 e.g. 2.7 V C3 = 330 F + VIN (Input Voltage) (0.9..1.5 V) C1 = 330 F (low ESR) DCSG1 + MAS 3587F VSS, XVSS DCEN DCSO2 D Power-On Push Button L2 = 22 H D2, Schottky VSENS2 VDC2 e.g. 2.5 V/3.5 V + Star Point Ground Connection very close to Pins DCSG1 and DCSG2 A D C2 = 330 F (low ESR) DCSG2 VREF AVSS0/1 A Fig. 4-35: External circuitry for the DC/DC converters 82 Micronas PRELIMINARY DATA SHEET MAS 3587F Micronas 83 MAS 3587F 5. Data Sheet History 1. Preliminary data sheet: "MAS 3587F MPEG Layer 3 Audio Encoder/Decoder", July 9, 2001, 6251-542-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: "MAS 3587F MPEG Layer 3 Audio Encoder/Decoder", Nov. 7, 2001, 6251-542-2PD. Second release of the preliminary data sheet. Major changes: - definition of ambient operating temperature range TA specified PRELIMINARY DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-542-2PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 84 Micronas |
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